標題: 生醫應用系統單晶片之FPGA 實現
FPGA Implementation of Biomedical Application SoC
作者: 楊寓鈞
Yang, Yu-Chun
林進燈
Lin, Chin-Teng
電控工程研究所
關鍵字: Radix-22 FFT;定點數;ICA;生醫訊號;SDRAM控制器;VGA控制器;Radix-22 FFT;fixed-point;ICA;biomedical signal;SDRAM controller;VGA controller
公開日期: 2008
摘要: 在目前生醫電子領域研究中,如何能夠即時處理與分析大量的生理訊號是一個重要的討論問題。以往電子醫療和分析儀器都相當龐大且價格貴,因此可攜式與嵌入式的生醫電子產品,需求日益增加。基於這兩個原因,本論文提出生醫應用系統單晶片的設計,以提供資源整合性的使用。 本論文提出一個生醫訊號處理的系統單晶片設計,具有(1)可程式化的監控與分析生理訊號能力及(2)整合性硬體擴充的空間:只要配置好暫存器存取位址,便能將客製化硬體設計透過系統匯流排整合進系統中。此系統單晶片架構包含可程式化的中央處理器、生醫訊號處理單元、系統匯流排、通訊和顯示介面。可程式化的中央處理器負責系統程序的排程和輸出入控制;生醫訊號處理單元能對生理訊號做訊號分離與分析的數位訊號處理核心;系統匯流排的設計能夠方便數位訊號處理IP 的加入與移除。 經由實驗的結果顯示,本論文所提出生醫系統單晶片架構能在FPGA 的平台上以100 MHz 執行頻率達到訊號即時分析與顯示解析波形的效果。因為透過硬體執行與其他高速DSP 的使用有很大的節省空間,如較少執行的週期、較低的功率消耗、減少PCB 設計的面積等。最後,本論文所提出的架構透過FPGA 實現並在Altera DE2 發展板展示,共使用29,640 邏輯單元。
In the study of biomedical electronics nowadays, processing and analyzing masses of physiological signals in time is a critical issue in real world. In the past, electronic treatment and analysis instruments are very expansive and large. Therefore, the requirement of portable and embedded biomedical electronic product is growing rapidly. Based on these two reasons, this thesis presents a system-on-chip (SoC) design for biomedical applications to provide the integration of systematic resources. In this thesis, the SOC design for biomedical signal processing is presented. It has the following features. (1) The ability of programmable monitoring and analyzing biomedical signals. (2) The flexibility for further hardware extension. The SoC design is composed of a programmable CPU, biomedical signal processing (BSP) units, system bus, communication, and display interface. The programmable CPU manages the process schedule and I/O control. The BSP unit is treated as digital signal processing (DSP) cores which can separate and analyze physiological signals. The system bus makes it flexible to add or to remove DSP IPs. By experimental results, the proposed design implemented on FPGA can achieve real-time analysis and waveform displays under at 100 MHz. Comparison with other high-speed DSP processors, the system presents some optimization such as less execution cycles, lower power consumption, use of fewer PCB area. Finally, the SoC design is demonstrated in this thesis with the Altera DE2 development board. The whole design is consisted of 29,640 logic elements.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079512538
http://hdl.handle.net/11536/41087
Appears in Collections:Thesis


Files in This Item:

  1. 253801.pdf