標題: 應用於MP3播放器訊號處理器之鎖相迴路式頻率合成器之設計
Design of PLL-Based Frequency Synthesizer for DSP in MP3 Player
作者: 高明正
Kao Ming Cheng
溫瓌岸
Kuei-Ann Wen
電機學院電子與光電學程
關鍵字: 鎖相迴路式頻率合成器;Programmable VCO
公開日期: 2007
摘要: MP3音樂壓縮格式具有極佳的方便性,被廣泛的應用在多媒體的播放與儲存,成為今日非常重要的一種數位音響壓縮標準。一個MP3播放系統,可以藉由軟體或硬體設計的方式來達到不同聲音取樣頻率的效果。對於手持式裝置來說,通常採用硬體設計的方式來實現,藉由調整數位訊號處理電路的操作頻率,可以完成此設計需求。除此之外,由於數位電路的消耗功率與操作頻率成正比,經由變頻操作的方式,也可以達到降低功率消耗的效果。本論文描述一個應用於數位訊號處理器之鎖相迴路式頻率合成器之設計。此設計提供了一個可程式化的輸出時脈,可以讓數位訊號處理器有不同的操作頻率。在輸出的時脈頻率較高的情況下,操作的速度快,效能也比較高。在輸出的時脈頻率較低的情況下,則是可以達到省電的效果。 此電路為一完全積體化的設計,採用0.18微米的製程技術。電路所使用的基本時脈是由一個24MHz的晶體震盪器所產生。再經由一個除頻器,將此24MHz的基本時脈做除頻,藉以產生鎖相迴路所需的參考頻率。除此之外,電路中還包括了一個可程式化的除頻器,藉此來合成所需要的輸出時脈頻率。此頻率合成器之合成頻率範圍為31.059MHz到81.882MHz。其工作電壓為1.8伏特,並且要能容許正負十個百分比的電壓誤差。此頻率合成器經過量測後,顯示其鎖相迴路在所有的輸出情況下皆可以正常的鎖住相位。當量測輸出時脈頻率為81.882MHz時,其時脈抖動為85ps,最大消耗電流為570μA。
MP3 compression format has been widely used in multimedia player and storage application for its convenient. It is an essential standard for digital audio compression nowadays. A MP3 player can implement different sampling rate in software or hardware design method. It is usually implemented in hardware design method especially for hand-held devices. It can be realized by adjusting the operating frequency of digital signal processing circuit. In addition, it will reduce the power consumption since the power consumption of digital circuit is proportional to operating frequency. In this thesis, the design of PLL-based frequency synthesizer for a digital signal processor (DSP) is described. It provides a programmable clock signal with variable frequency for DSP to operate in different condition. For higher speed and performance, a clock signal with higher frequency is used. For power saving requirement, a lower frequency clock signal is used. This circuit was fully integrated with a 0.18 μm 1P6M CMOS process. An 24 MHz crystal oscillator is used as a fundamental clock for this PLL. To generate the reference frequency for this PLL, a frequency divider is used to divide down the 24 MHz clock first. In addition, there includes a programmable frequency divider for frequency synthesizer. The frequency synthesizer is designed to generate a clock frequency from 31.059 MHz to 81.882 MHz. The supply voltage is 1.8 V with a ± 10% tolerance. The PLL has been tested and it can lock to all frequency range. The measured jitter is 85ps at 81.882 MHz, and the maximum current consumption is around 570uA.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009067508
http://hdl.handle.net/11536/41013
Appears in Collections:Thesis


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