標題: 一種新穎自行開發之快速精準量子模擬器用於三維度高應力下矽電洞能帶結構及反置層遷移率之研究
A New In-House Fast Sophisticated Quantum Simulator for Silicon Hole Band Structure and Inversion-Layer Mobility under Three-Dimensional GPa-Level Stresses
作者: 李建志
Lee, Chien-Chih
陳明哲
Chen, Ming-Jer
電子研究所
關鍵字: 量子侷限效應;機械應力;價電子能帶結構;六能帶 k•p 薛丁格波松方程自洽;Luttinger參數;Bir-Pikus形變電位參數;電洞遷移率;quantum confinement;mechanical stress;valence-band structure;six-band k•p Schrödinger-Poisson self-consistent method;Luttinger parameters;Bir-Pikus deformation potentials;hole mobility
公開日期: 2012
摘要:  對於持續微縮的電子元件,除了將會面對額外的量子侷限效應(不論是電場造成的量子侷限或是空間造成的量子侷限)之外,亦會面對複雜的機械應力(不論是有意或是無意的任何方向應力)。這兩個現象皆會對價電子能帶結構造成關鍵的影響,進而大大地改變電洞的電特性。換句話說,這將會在理論工作上造成額外的複雜程度和沉重的計算負擔。但是因為電洞特性的計算,例如電洞遷移率,完全根據價電子能帶結構來進行計算,所以並不意外,令人滿意的電性計算結果需要精細和高品質的價電子能帶結構計算來達成。此論文聚焦在電子元件p型反置層中的電洞特性,而我們自行開發的模擬器是根據六能帶k•p薛丁格∙波松方程自洽方法來達成。 此論文主要的目的是:研究在顯著的量子侷限效應和複雜的應力影響下矽的反置層電洞特性。而根據此主題,論文的組織結構如下。首先,我們將介紹在p型反置層中價電子能帶結構。接下來,聚焦於p-NEP 的數值計算方法和物理模型,然而根據p-NEP的數值演算方法,電腦處理器計算時間會非常地漫長。因此,我們提出一個新穎的演算加速器,能本質地提升六能帶k•p薛丁格∙波松的自洽模擬速度。此演算加速器是經由一個三角位能井為主的六能帶k•p模擬器,一個電洞等效質量近似技巧,和一個與導帶電子版本相近的薛丁格∙波松自洽計算器所組成。加速器會輸出一個接近實際量子侷限靜電位能的初始解,且對不同的溫度、不同基板參雜濃度、反置層電洞濃度和表面晶格方向皆可行。其他論文發表的計算是支持我們(001)和(110)基板晶格方向的計算結果。全部的電腦處理器計算時間被減少到接近8%沒有加速器的計算時間。加速器更普遍的應用也會在此說明。 接著,根據三組互異並以塊材為導向的Luttinger參數γ1, γ2, 和γ3,以塊材為導向的Luttinger參數在六能帶k•p薛丁格∙波松方程自洽方法的可行性被確認。以塊材為導向的Luttinger參數計算,(110)基板方向p型場效電晶體之實際電洞子能帶結構可以被良好地重現,並與最近Takahashi等人的Shubnikov-de Haas (SdH)迴旋共振實驗比較。 更進一步,沿著三個晶格方向的單軸GPa等級應力造成的電洞遷移率變化可以分為四個分別的貢獻來討論:一、聲子震盪限制,二、表面粗糙限制,三、散射時間限制,四、傳導質量限制下的遷移率變化。在同一討論中,我們致力研究應力相關的三個材料參數,也是所謂的Bir-Pikus形變電位參數a□, b, 和d。並且,在數值上有著廣闊的分布。為了克服如此明顯的不一致性,我們詳盡地計算電洞反置層遷移率,發現了沿著單軸<110>方向的壓縮應力對電洞遷移率增加而言,a□ 影響微弱,b影響適中,而d影響劇烈。以上的結論提供了指引透過實驗決定主要參數d,次要參數b,及一般使用的a□數值。另外,p-NEP的使用者介面(UI)和模擬程序會示範操作,模擬的子能帶結構、臨界電壓、電容和閘極直接穿隧電流會被討論。最後,我們將總結研究結論。
The continuously scaled electronic devices encounter not only the extra quantum confinement (no matter from the field confinement or from the space confinement) but also the complicated mechanical stresses (no matter the intentional or unintentional stressors along the arbitrary directions). Both of these two phenomena cause the crucial impacts on the valence-band structure which can greatly alter the hole electrical properties. In other words, these lead to the extra complexities and the heavy computation burden in the theoretical work. Since the evaluation of the hole electrical properties such as hole mobility fully rely on the valence subband structures, with no surprise the precise and fine quality of valence subband structures are urgently required to achieve the satisfactory calculations. With the six-band k•p Schrödinger-Poisson self-consistent method this dissertation will focus on the hole electrical properties in p-type inversion layer of the electronic devices via the self-developed simulator, p-NEP (abbreviation of p-type Nano Electronics Physics). The main purpose of the dissertation is to investigate the hole electrical properties in silicon inversion layer beneath on the significant quantum confinement and the complicated mechanical stresses. Based on this main topic, the organization of this dissertation is described below. First, an introduction to the valence band structures in p-type inversion layer is described. Then, the dissertation is focused on the numerical techniques and physical models of p-NEP. However, according to the algorithm of p-NEP, the CPU time is extraordinarily long. To overcome the issue, we present a novel computational accelerator to intrinsically boost a self-consistent six-band k•p Schrödinger-Poisson simulation. This accelerator comprises a triangular potential based six-band k•p simulator, a hole effective mass approximation (EMA) technique, and an electron analogue version of the self-consistent Schrödinger and Poisson’s equations solver. The outcome of the accelerator furnishes the initial solution of the confining electrostatic potential and is likely to be close to the realistic one, valid for different temperatures, substrate doping concentrations, inversion hole densities, and surface orientations. The results on (001) and (110) substrates are supported by those published in the literature. The overall CPU time is reduced down to around 8% of that without the accelerator. The application of the proposed accelerator to more general situations is projected as well. Secondly, according to three distinct sets of the bulk oriented Luttinger parameters γ1, γ2, and γ3, the validity of the bulk oriented Luttinger parameters in the six-band k•p Schrödinger-Poisson self-consistent method is confirmed. With the the bulk oriented Luttinger parameters, the realistic hole subband structures in (110) p-MOSFETs can be well reproduced in comparison with the recent Shubnikov-de Haas (SdH) oscillation experiment by Takahashi, et al. Thirdly, the hole mobility change for GPa-level uniaxial stresses along each of three crystallographic directions are distinguished into four contributing componds: (i) phonon-limited, (ii) surface-roughness-limited, (iii) scattering-time-limited, and (iv) conductive-mass-limited mobility changes. It is also dedicated to three key strain-related material parameters, namely the Bir-Pikus deformation potentials a□, b, and d, which are widespread in magnitude. To improve such large discrepancies, we conduct sophisticated calculations on <110>/(001) and <110>/(110) hole inversion-layer mobility. We find that, to affect the calculated hole mobility enhancement, a□ is weak, b is moderate, and d is strong, particularly for the uniaxial compressive stress along the <110> direction. This provides guidelines for an experimental determination of the primary factor, d, and the secondary factor, b, with the commonly used values for a□. The user interface (UI) and simulation process of p-NEP are further demonstrated. The resulting subbnad structures, threshold voltage, capacitance, and gate direct tunneling current are all addressed. Finally, we summarize the conclusions of our works.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079311538
http://hdl.handle.net/11536/40481
Appears in Collections:Thesis


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