標題: 鎖相迴路時脈抖動之內建自我測試
Built-In Self-Tests for Jitter Measurement of Phase-Locked Loops
作者: 徐仁乾
Hsu, Jen-Chien
蘇朝琴
Su, Chau-Chin
電控工程研究所
關鍵字: 內建自我測試;抖動;時脈抖動;鎖相迴路;展頻時脈;BIST;jitter;clock jitter;phase-locked loop;spread-spectrum clock
公開日期: 2009
摘要: 資料傳輸之品質受到時脈抖動之影響甚巨,然而針對時脈抖動的量產測試卻因成本過高而難以實現,因此,時脈抖動的內建自我測試電路成為量產測試的一個解決方案。時脈抖動的內建自我測試電路一般皆透過時間對數位轉換器來完成,將時脈抖動轉換成為數位訊號,以低速數位訊號的方式提供量測機台進行量測,因此一個良好的時間數位轉換器是內建自我測試的重要元件。在本論文中,我們提出了三種不同的時間對數位轉換器以及內建自我測試電路,第一種是針對電荷幫浦式鎖相迴路的時脈抖動量測所設計,它使用了新穎的高解析度時間對數位轉換器,可將受測電路本身的元件重複利用做為時間對數位轉換器的一部份,因此縮小了額外的電路面積。量測結果顯示其量測解析度可以達約兆分之一秒,而量測誤差小於百分之二十。第二種內建自我測試電路是針對展頻時脈鎖相迴路所設計,它可分離展頻時脈的低頻調變訊號以及高頻的時脈抖動訊號,同時建立一時脈抖動的估算方式,以驗證此電路的可行性。我們實做了一個時脈頻率每秒十二億次、十個相位的鎖相迴路以及時脈抖動量測電路,並比對量測結果與估算值,顯示量測誤差低於0.0026個單位區間。第三種內建自我測試電路可量測資料與時脈回復電路的時脈抖動,並依據所量得之結果,估算資料之位元誤差率,這種內建自我測試電路不需高解析度的延遲訊號線即可達到高精準度的量測結果,它利用校正的機制和曲線對應的方式獲得高精準度。校正的機制是將壓控震盪器切換至自由震盪模式,以機率統計的方式獲得時間對數位轉換器中延遲緩衝器的延遲時間。此內建自我測試電路還可透過曲線對應的方式分離不同類別的時脈抖動,以預估在位元誤差率為兆分之一的系統規格上的總時脈抖動大小。
Signal quality of data transmission is significantly affected by clock jitter of Phase-Locked Loops (PLLs). However, production test for clock jitters is too expensive to implement. Built-In Self-Test (BIST) for clock jitter measurement becomes an alternative solution for production test. Basically, BIST methodologies are based on Time-to-Digital Converters (TDCs) which convert phase differences of a tested clock and a reference clock into low-speed digital signals for test equipments to measure. In this thesis, we proposed three kinds of TDCs and BIST circuits for different applications. The first one is designed for measuring clock jitter of charge-pump PLLs. The BIST is based on a novel high resolution TDC. Small area overhead is achieved by reusing the Voltage-Controlled Oscillator (VCO) and loop filter of the tested PLL as part of the TDC. The experiment result shows that the resolution is about one pico-second and the measurement error is smaller than 20%. The second BIST circuit is proposed for measuring timing jitter of Spread-Spectrum Clocks (SSCs). The BIST circuit can separate low-frequency phase drifting caused by frequency modulation and high-frequency jitter. Because of lack of dedicated instruments for SSC timing jitter measurement, a jitter estimation method is also developed for validating the feasibility of the BIST circuit. A 1.2GHz 10-phase Spread-Spectrum Clock Generator with a jitter measurement circuit is designed and fabricated. The experimental results show that the proposed built-in measurement approach has an error of less than 0.0026UI. The third BIST circuit is developed for testing the relative timing jitter of data and clock recovery circuits. This BIST circuit doesn’t need a high resolution delay line to achieve high accuracy measurement result, but uses calibration and curve-fitting algorithms. Calibration is done by switching the VCO of the tested PLL into free-running mode and using statistical theories to acquire accurate delay time of the delay buffers in the TDC. This BIST circuit also separates deterministic jitter and random jitter by adopting the bathtub curve-fitting algorithm and estimates total jitter at bit-error rate=10-12 level.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079212805
http://hdl.handle.net/11536/40361
Appears in Collections:Thesis


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