DESIGN AND ANALYSIS OF HIGH FREUQNCY CMOS FRONT-END RECEIVER CIRCUITS
|摘要:||在無線傳輸領域，從以前傳輸文字、檔案，到近期即時影像的傳輸，其無線傳輸的資料量大幅的提升，無線網路的傳輸頻率也因此逐漸地往高頻提升以滿足龐大的資料量，在近距離一百公尺內資料傳輸主要從傳統的802.11 a/b/g/n (2.4兆赫) 到802.11 ac (2.4及5兆赫) 發展至 802.15 (60兆赫超寬頻)及W-band (75~110兆赫超寬頻)，而在雷達領域為了自動駕駛的目的，頻段也從24兆赫提升到77兆赫，在傳統上，較高頻的電路因為需要較高的元件特性，因此主要由特殊製程來實現，如GaAs…等，因此其成本也相對提高而無法普及。但隨著普及互補式金氧半積體技術的提升，場效電晶體的截止頻率逐漸由幾十兆赫推上百兆赫，近年來較高頻之射頻電路也逐漸可由此製程來實現，來達到低成本的需求進而普及，為了達成操作於高頻之目的，許多所提出之電路功率消耗相當大。而本論文利用此互補式金氧半積體製程技術來實現未來較常用之接收器電路，並且其功率消耗街亦相當低，在電路部分主要包括有低雜訊放大器，混頻器，壓控震盪器, balun及中頻放大器。
首先，本論文提出一個適用於高頻低雜訊放大器之電路架構，主要可以增加場效電晶體之截止頻率，亦可以增加低雜訊放大器之隔絕來減少在高頻下非理想的效應，因此可以獲得較好的增益特性，此外。採用上述之電路架構，一個低雜訊放大器採用了0.18微米的金氧半製程來設計與製作適用於24兆赫車用雷達系統，其面積為0.77 x 0.84 □m2。由量測的結果可知，在1伏特電壓下操作，功率消耗14毫瓦，增益10.1 dB，雜訊指數3.8 dB。
其次，本論文提出了一個適用於77兆赫車用雷達接收器，其前置接收器整合了兩級低雜訊放大器，二階次諧波混頻器，壓控振盪器、中頻放大器及balun。此接收器採用本論文所提出之方式設計77兆赫低雜訊放大器，為了減少整合接收器的困難度及功率消耗在混頻器採用了二階次諧波的方式，此外在低雜訊放大器與混頻器直接利用balun的將單端的射頻訊號轉換成雙端輸入混頻器。此接收器以採用0.13微米的金氧半製程來設計與製作，面積為1150×1050 □m2。由量測的結果可得知，此接收器功率在電壓1伏特下功率消耗為13.5毫瓦，當中頻頻率200百萬赫時，增益有21.8 dB，當中頻頻率在1 兆赫時，增益11.8 dB，此雜訊指數為14.5 dB。
此外，本論文提出一個51.6-55兆赫前置接收器，此接收器整合了一個新提出之三階次諧波混頻器，此接收器亦整合了一個寬頻的低雜訊放大器、九十度相位差之壓控振盪器，中頻放大器及輸出緩衝器。採用三階次諧波混頻器主要有低LO漏電流至RF輸入端因而有較低的直流偏移。然而，此晶片益整合了一個寬調整範圍之壓控振盪器，由於採用三階次諧波混頻器，LO之頻率可以減少三倍，除了可以減少壓控振盪器之功率消耗，亦可擴大其有效的調整範圍，使在高頻且寬頻之電路，更容易達成整合的目的。所提出之接收器已使用0.13微米的金氧半製程來設計與製作，面積為1385×1070 □m2，由量測結果得知，其功率消耗為32.38毫瓦，壓控振盪器提供了從17.2到21.4兆赫寬調整範圍的特性。在51.6到55兆赫，此接收器之增益可維持高於21 dB，且雜訊指數可低於18.1 dB。
最後，本論提出一個78~102兆赫前置接收器，超寬頻的需求使得設計上不僅在電路上在架構上更有具挑戰性，此接收器整合了一個超寬頻低雜訊放大器、混頻器及中頻放大器，為了達到寬頻的目的，此低雜訊放大器在架構上採用三級放大器，並將三級放大器中心頻率分別設計於不同頻路上以增加其頻寬。將中心頻率較高之放大器安排置第一級以達到增加高頻增益的目的，將中心頻率較低頻率之放大器安排至最後一級以減小整合的困難度。第一級電路採論文中所提出之低雜訊放大器架構。為了減少整合上之困難度，在混頻部分採用二階次諧波方式。此架構採用90次微米的金氧半製程來設計與製作，面積為680×1020 □m2。經由量測結果可得此接收器，在1.2伏特電壓操作下，其功率消耗為18.6毫瓦，其3-dB頻寬可由78~102兆赫。當中心頻率在94兆赫時，有最大增益11.8 dB，雜訊指數為13.4 dB。
In wireless communication, the data-rate requirement is significantly increasing from the text/file delivery until the real-time image communication. The frequency is rapidly moving to the high frequency for demand of high-data rate. For high-date rate requirement, the standard of short-distance data communication is presented, such as 60-GHz system (IEEE 802.15) and W-band system, in place of 2.4-GHz system (IEEE 802.11 a/b/g/n) and concurrent system of 2.4-GHz and 5-GHz frequency. In the vehicle radar system, the operation frequency is also push up to 77 GHz. Traditionally, these high frequency systems are realized by expensive process, like, GaAs..., because of high performance of the device in these expensive process. Thus these circuits are very difficult to be popularized. Fortunately, the performance of popular CMOS process is also rapidly improving. In advance CMOS process, the cut-off frequency is reaching up than 100 GHz. Recently, the CMOS high frequency circuits are gradually realized in order to decrease the cost. However, some of these circuits is very power hungry for operating in high frequency operation. In this thesis, we design several receivers with rather low power consumption for recent proposed high frequency application. In these receivers, the circuits are including low noise amplifier, mixer, voltage control oscillator, balun and IF amplifier. At first, a new structure to implement the low noise amplifier suitable for high frequency operation. In this technique, the enlarger cut-off frequency of FET and good-isolation can be reached. Thus the gain of low noise amplifier can be boosted. A CMOS 24-GHz low noise amplifier for vehicle radar application has been designed and fabricated in CMOS 0.18-□m process with a chip area of 0.77 x 0.84 □m2. From the measurement results, this amplifier has gain of 10.1 dB, noise figure of 3.8 dB and the power consumption of 14 mW from 1-V supply voltage. Secondly, a CMOS 77-GHz front-end receiver for vehicle radar application is presented in this thesis. This front-end receiver is consisted of a two-stage low noise amplifier, a second-order sub-harmonic mixer, a voltage control oscillator, a balun and a intermediate frequency amplifier. The proposed structure of low noise amplifier is redesign in 77 GHz. In order to decrease the integrating difficulties and the power consumption, the traditional mixer is replaced by the second-order sub-harmonic mixer. Besides, a single-end radio frequency output signal of low noise amplifier is transformed to two differential-end signals in order to fed into the second-order sub-harmonic mixer through the balun. This receiver has been designed and fabricated in CMOS 0.13-□m process with a chip area of 1150×1050 □m2. From the measurement results, with intermediate frequency of 200 MHz, this receiver has a gain of 21.8 dB. By increasing the intermediate frequency to 1 GHz, this receiver has a gain of 11.8 dB with a noise figure of 14.5. The power consumption is 13.5 mW from the 1-V supply voltage. A 51.6-55-GHz CMOS receiver front-end designed with new third-order sub-harmonic mixer and on-chip wide-tuning-range VCO is proposed, analyzed, and fabricated for millimeter-wave (MMW) UWB applications. The proposed receiver consists of a broadband-matching LNA, active sub-harmonic mixers, a quadrature VCO, IF amplifiers, and output buffers. The use of third-order sub-harmonic mixer has advantages of low LO leakage to RF ports, low DC offset, and low gain/phase mismatch. Moreover, the wide-tuning-range quadrature VCO integrated on the same chip to cover the full UWB bandwidth and decrease power dissipation. The proposed receiver is fabricated in 130-nm CMOS technology with a chip area of 1385 □m × 1070 □m and low power consumption of 32.38 mW. In addition, the integrated VCO provides a wide tuning range from 17.2 GHz to 21.4 GHz (21.7%). The simulated LO leakage to RF posts is below -40 dB. Within the 3-dB bandwidth of 51.6 to 55 GHz, the gain of receive is maintained above 21 dB and noise figure is below 18.1 dB. Finally, a CMOS 78~102 GHz front-end receiver is presented in this thesis. The demand for high frequency and ultra-wide band has larger challenges not only in the circuits but also in the architecture. The proposed receiver is consisted of a broadband low noise amplifier, a second-order sub-harmonic mixer with a intermediate frequency amplifier. In order to suffice for the requirement of ultra-wide band, the three stage low noise amplifiers have been integrated in this receiver. The frequency of maximum gain in each stage is made an arrangement in differential frequency for extending the bandwidth of low noise amplifier. Within the bandwidth, the highest peak-gain frequency stage is in the first to boost the gain of highest frequency, and the lowest is in the last stage to reduce the difficulties in the integration. In order to decrease the integrating difficulties and the power consumption, the traditional mixer is replaced by the second-order sub-harmonic mixer. This receiver has been designed and fabricated in CMOS 90-nm process with a chip area of 680×1020 □m2. From the measurement results, this receiver has a power consumption of 18.6 mW from 1.2-V supply voltage, a ultra-wide 3-dB bandwidth of 78-102 GHz. When the intermediate frequency is at 1 GHz, the receiver has a maximum gain of 11.8 dB with a noise figure of 13.4 under the radio frequency is at 94 GHz. In this thesis, the several high frequency receivers have been designed and fabricated in CMOS process. In order to enhance the performance and reduce the power consumption, a new low noise amplifier has been proposed in this thesis, and sequentially designed in 24-GHz, 77-GHz, 51.6-55-GHz and 78~102-GHz systems. Besides, the high frequency, low power dissipation and high integration are achieved in proposed receivers of this thesis. In the future, these receivers can be optimized for the variation of corner and temperature and integrated with baseband circuits to become a more complete system.
|Appears in Collections:||Thesis|