The Fabrication and Characterization of Schottky Barrier Thin Film Transistor with Field-Induced-Drain
|關鍵字:||薄膜電晶體;蕭特基接面;場引效汲極;熱離子發射;場發射;鰭狀電晶體;全能障內缺陷態位密度;場效電導法;Thin Film Transistor;Schottky Contacy;Field-Indiced Drain;Thermionic Emission;Field Emission;FinFET;Full Band-Gap Density of Defects;Field Effect Conductance Method|
Abstract Schottky Barrier MOSFET is simpler in processing and inherently suitable for low temperature processing. It is also capable of ambipolar operation and short channel control. However, it suffers from deleterious off-state leakage current. If the shortcomings of SB-MOSFET could be improved, the inherent ambipolar property of SB-MOSFET will make fabrication process and circuit design more flexible. If the idea is applied to thin film transistors, the low process temperature of metallic junction formation will make SB-TFT compatible with middle temperature active matrix liquid crystal display (AMLCD) manufacture. In addition, salicidation process will not only reduce the thermal budget, but also decrease the source/drain parasitic resistance. This is quite appropriate for low temperature poly-Si application. In this dissertation, a novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension was proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying over the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main-gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from the low on/off current ratio, the new device exhibits high on/off current ratio of up to 106 for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS processes integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications. Second, we have experimentally investigated the conduction mechanisms of the off-state leakage current for Schottky Barrier TFTs with FID and conventional structure. The results show that the activation energy of the off-state leakage decreases significantly with increasing úVGD êfor SBTFT with conventional structure. This indicates that field-emission conduction plays a major role as the field strength in the drain junction becomes high, and results in the strong GIDL-like phenomenon. In contrast, the activation energy of the off-state leakage shows only minor dependence on VGD for SBTFT with FID. This is ascribed to the fact that the high-field region can be pulled away from the silicided drain for the FID structure. As a result, the field-emission conduction will be eliminated, and thus the GIDL-like leakage current can be effectively suppressed. Next, SBTFT devices with ELA poly-Si active channel were successfully fabricated. Excellent device performance in terms of steep subthreshold slope and high on/off current higher than 108 for both p- and n-channel operations are demonstrated, for the first time, on a single poly-Si TFT device. Source-side tunneling process is found to be important for device operation, especially for the n-channel operation that has a larger barrier height. The stellar performance with on/off current ratio larger than 108 for both n- and p-channel modes of operation, together with its inherent ambipolar capability, implantless process, silicided source/drain, low thermal budget, and simplified CMOS integration scheme, makes this kind of device a promising candidate for future AMLCD and SOP applications. Applications of nano-scale device are very popular nowadays. We will show that the ambipolar performance of SB poly-Si TFTs can be improved by scaling the channel width into the nano-scale regime. Our results indicate that, despite the high trap density in poly-Si films, high on/off current ratio and small subthrehold swing can be achieved. It appears therefore possible to achieve SOI-like device characteristics if poly-Si film improvement methods, such as excimer laser annealing and metal-induced crystallization scheme, are adopted. Finally, we proposed and successfully demonstrated a novel approach to obtain the full band-gap DOS in the channel of TFT devices. In this approach, the field-effect conductance method is performed on an SB poily-Si TFT which has the capability of ambipolar operation. Both incremental and temperature methods are adopted on the SB and conventional implanted devices to construct the relationship between DOS and the energy level in the gap. For devices with the same channel material, the results are in good agreement among the different extraction schemes, indicating the novel approach is very reliable. We have also characterized the dependence of both electrical and structural parameters on the measurement results in order to set suitable test conditions. Our results indicate that the parasitic resistance presenting in the channel would result in the overestimation of tail state density. A sufficiently high drain and sub-gate biases and short electrical junction length are thus needed. In addition, for reliable full band-gap DOS analysis, near-mid-gap silicide material like CoSi2 is desirable. In addition, the effect of process treatment like the re-crystallization and plasma hydrogenation steps on the DOS characteristics has also been characterized. Their impacts are clearly identified using the new approach. Benefits of using a nano-scale fin channel for promotion of the controllability of gate voltage over the channel potential is also clearly demonstrated. Finally, we show that the flat-band voltage could be obtained by simply measuring the gate voltage at the intersection point of p- and n-mode I-V curves. The overall process is thus greatly simplified and cost-saving comparing to conventional approach, since only one device and two I-V measurements performed at room temperature are needed. We strongly believe that the novel method is extremely useful for practical applications.
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