標題: 低功率正反器之設計應用於晶片網路以及維特比解碼器
Ultra Low Power Flip Flop Design for Network-on-chip and Viterbi Decoder Application
作者: 王尹伶
黃威
電機學院IC設計產業專班
關鍵字: 正反器;低功耗;串列器;維特比解碼器;flip flop;low power;serializer;viterbi decoder
公開日期: 2008
摘要: 本論文使用低功耗電路設計的技術,來實現時脈驅動儲存元件之設計。一個適合應用在低震盪電壓時脈的邊緣觸發正反器(LCSFF)被提出,且使用UMC 90nm標準元件的技術來設計以及佈局。此單緣觸發正反器使用了低電壓的時脈震盪延遲電路,來產生操作的觸發波形和電晶體疊加技術,來達到減低漏電流的低功耗設計。 此一低震盪電壓時脈正反器,非常適用應用於需要大量儲存單元的系統。本論文中將把此正反器應用在晶片網路□的串列器以及解串列器,還有維特比解碼器□的記憶殘存單元。根據模擬結果顯示,這樣的應用可以減少至少27.5%的功率消耗。
The clocked storage elements using the low power technique are realized in this paper. The low clock swing edge-triggered flip-flop (LCSFF) suitable for the low switching activity applications is proposed and simulated in UMC 90nm technology, and layout in UMC 90nm standard cell. The single edge-triggered flip-flop uses low swing voltage delay chain generating the operation transparency window for reduces the power consumption. The flip-flop uses the power gating technique to reduce the leakage current. The low clock swing flip-flop (LCSFF) suitable for the system which used a great quantity of memory. In this thesis it applies to the serializer and deserailizer in network on chip and the survivor memory unit in viterbi decoder. The simulation result shows the applications could save more than 27.5% power.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009595504
http://hdl.handle.net/11536/40129
Appears in Collections:Thesis


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  1. 550401.pdf