標題: 32位元雙軌之靈活的運算邏輯單元實作
A Flexible Dual-rail 32-bit ALU Design
作者: 方秋鈞
陳昌居
Chang-Jiu Chen
資訊科學與工程研究所
關鍵字: 靈活之非同步邏輯運算單元;flexible asynchronous ALU
公開日期: 2007
摘要: 通常來說ALU對於處理器的效能是個瓶頸,所以能夠有效提升ALU的效能對於處理器整體效能的提升有一定的幫助。然而在同步電路設計上,整體的速度往往是由最慢的元件所決定。但是對於非同步電路設計而言,再前一筆資料處理完之後便能立刻去處理下一筆需要處理的資料。所以整體效能是隨著資料的複雜性而有所不同而不會綁在最長的延遲時間上,因此效能上較趨向於平均延遲時間而非最長延遲時間。 於是在本篇論文中便引入非同步電路設計的概念來幫助我們提升ALU的效能。而其構想是來自於DSP處理器中常用到的MAC指令。MAC指令是一個先做乘法再將所得的結果作加法的兩階段指令。我們將此想法加以應用並設計一個包含兩個階段的ALU。此設計的優點在於其指令格式和延遲時間上更具有彈性。
Because ALU usually is the bottleneck of the processor performance, improving the processing time of ALU is also the chance to improve overall performance. In synchronous circuit design, the performance is determined by the slowest component. However, in an asynchronous circuit design, the next computation step can be started immediately after previous step has been completed. Thus in this thesis we introduce the concepts of asynchronous circuit design to improve performance of ALU. The original idea of our design is derived from MAC related instruction supported by almost all DSP processors. Then we extend this idea to design our ALU composed of stages. The advantage of this kind of design is its flexibility on instruction types and delays.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009555630
http://hdl.handle.net/11536/39581
Appears in Collections:Thesis


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