標題: 應用於三維繪圖系統之可重組式深度緩衝區壓縮演算法設計與實作
Reconfigurable Depth Buffer Compression Design and Implementation for 3D Graphics System
作者: 鍾宗融
Tzung-Rung Jung
范倫達
Lan-Da Van
資訊科學與工程研究所
關鍵字: Depth Buffer;3D Graphics System;Reconfigurable Architecture;Compression Algorithm;深度緩衝區;三維繪圖系統;可重組式架構;壓縮演算法
公開日期: 2008
摘要: 在本論文中,我們針對三維繪圖處理器中的深度緩衝區提出具減少頻寬需求與可重組式的壓縮演算法;根據不同的場景,從十一種壓縮模式中選擇出最適合的壓縮模式,而這十一種模式是由2-bit DDPCM、1-bit HA、7-bit DDPCM三種壓縮演算法所組合而成。此外,我們所提出的演算法亦支援單平面與雙平面兩種型態方塊,並能支援四種差值組合方式。在8x8大小方塊而且深度值長度為16-bit的Teapot 場景模擬環境下,我們提出的演算法其平均壓縮比可達1.75,而且相較於HA 與DDPCM壓縮方法能夠分別改善13.6%與31.6%;在8x8大小方塊而且深度值長度為16-bit的Stereoscopic polygons 場景模擬環境下,我們提出的演算法其平均壓縮比可達1.74,而且相較於HA 與DDPCM壓縮方法能夠分別改善21.7%與38.1%。 深度緩衝區壓縮演算法其架構具可重組式與可調式功耗之特色,使用的製程為TSMC 0.18-um CMOS process,其晶片所佔面積為1.13 mm2;在操作頻率為100 MHz與操作電壓為1.8伏特的情況下,未壓縮模式的最大功率消耗為38.63 mW,單平面模式下的最大功率消耗為22.75 mW,雙平面模式中(僅包含rising, vertical, and horizontal cases)的最大功率消耗分別為51.76/56.25/71.9 mW,雙平面模式中(僅 包含falling cases)的最大功率消耗為57.63 mW。
A less-bandwidth-required reconfigurable depth buffer compression algorithm and the corresponding power-efficient architecture have been developed for 3D graphics system. The proposed algorithm is able to adaptively compress the depth buffer data according to different-scene changes by employing 11 compression modes generated from three compression algorithms including Differential Differential Pulse Code Modulation (2-bit DDPCM), Hasselgren and Akenine-Moller’s (1-bit HA), and 7-bit DDPCM schemes. Furthermore, this reconfigurable algorithm supports one-plane and two-plane type and four kinds of combination cases. For 8x8 tile size with 16-bit depth values under the teapot benchmark, the proposed reconfigurable algorithm can achieve CR of 1.75 on average and improve 13.6% and 31.6% compared with the HA and DDPCM compression methods, respectively. For 8x8 tile size with 16-bit depth values under the Stereoscopic polygons benchmark, the proposed reconfigurable algorithm can achieve CR of 1.74 on average and improve 21.7% and 38.1% compared with the HA and DDPCM compression methods, respectively. The proposed reconfigurable power-efficient depth buffer compression architecture has been verified and implemented in TSMC 0.18-um CMOS process. The core area is of 1.13 mm2. The maximum power consumption of 38.63 mW in uncompression mode, 22.75 mW in one-plane type, 51.76/56.25/71.9 mW in two-plane type, including rising, vertical, and horizontal cases, and 57.63 mW in two-plane type, including falling cases, can be achieved at 100 MHz and with the supply voltage of 1.8V.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009555629
http://hdl.handle.net/11536/39579
Appears in Collections:Thesis


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