標題: 鎖相迴路軟體化之研究
The Study of Software-defined Phase-locked Loop
作者: 莊承穎
Cheng-Ying, Chuang
許騰尹
Terng-Yin Hsu
資訊科學與工程研究所
關鍵字: 軟體鎖相迴路;鎖相迴路;全數位鎖相迴路;Software-defined Phase-locked Loop;Phase-locked Loop;all-digital phase-locked loop
公開日期: 2007
摘要: 這篇論文主要實作軟體鎖相迴路的平台,在此平台中結合了OPEENRISC和全數位鎖相迴路的特性與功能。實作此平台總共有三個主要設計議題,分別是溝通介面的建築、以智財(IP)為基礎的電路設計和軟體演算法的開發。在介面上特別用於同步、通訊和控制。在智財(IP)為基礎的電路裡,本論文著重於開發時間數值轉換器(全數位鎖相迴路中的模組),在不需要寄生電容跟寄生電阻的效應的情況下,設計出精準度高達1ps的時間數值轉換器。在軟體演算法的執行上,主要是在演算法執行的週期數目作出最佳化,在此平台上所執行的演算法,鎖定頻率跟相位,共需5個週期。 這個平台在重複利用上、製程轉移上和彈性上都有很好的表現,可以去縮減設計成本,特別是時間上的成本。最後,這個平台是完整的建立在 Faraday 90nm 製程下,可以完整運作。
This paper is proposed to the platform of software defined phase locked loop. The platform is combined of OPENRISC and the all-digital phase locked loop. There are three major issues in this platform: the interface, the intellectual property (IP) based design and the software algorithm. First, the interface is used for synchronization, communication and controlling. Second, the time-to-digit converter is one of IP in the all-digital phase locked loop. We propose the time-to-digit converter which resolution is 1ps without the parasitical capacitance and parasitical resistance. Finally, the topic of software algorithm is the cycle count. The platform needs 5 cycles to lock the frequency and the phase. This platform has good performance at the reusability, the process portability, and flexibility. The platform can reduce the design cost, especially at time. We implement this platform on Faraday 90nm process.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009555627
http://hdl.handle.net/11536/39577
Appears in Collections:Thesis


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