Title: A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration
Authors: Lee, Zwei-Mei
Wang, Cheng-Yeh
Wu, Jieh-Tsorng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: analog-digital conversion;calibration;sample and hold circuits
Issue Date: 1-Oct-2007
Abstract: A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.
URI: http://dx.doi.org/10.1109/JSSC.2007.905293
http://hdl.handle.net/11536/3930
ISSN: 0018-9200
DOI: 10.1109/JSSC.2007.905293
Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 42
Issue: 10
Begin Page: 2149
End Page: 2160
Appears in Collections:Conferences Paper


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