標題: 考慮製程變異與溫度效應的三維積體電路功率最佳化方法Power Optimization in 3D ICs Considering Process Variations and Thermal Effect 作者: 于斯安Shih-An Yu李育民Yu-Min Lee電信工程研究所 關鍵字: 三維積體電路;製程變異;溫度效應;功率;最佳化;3D IC;Process Variations;Temperature Effect;Power;Optimization 公開日期: 2007 摘要: 三維積體電路被視為一個有效的方法來解決二維積體電路上過長導線造成的進步瓶頸，但是過高的溫度也成為三維積體電路的挑戰。晶片上的溫度會對效能造成嚴重的影響，因此有必要降低電路的功率消耗。同時，另一個在奈米製程中，對電路設計有重大影響的議題則是製程變異。在這篇論文中，我們提出一個利用雙電壓源的統計型方法來降低三維積體電路上的總功率消耗。利用卡洛展開(Karhunen-Loeve expansion)將通道長度(channel length)和氧化層厚度(oxide thickness)這類具有空間相關隨機過程的物理參數轉換成一組無相關性的隨機變數。因為製程變異的關係，晶片上的靜態功率是一個隨機過程，我們利用一個統計型的溫度分析方法來得到溫度平均值跟變異量的分布。為了強調溫度的影響，我們採用具溫度相關性的漏電流(leakage current)與邏輯閘延遲(gate delay)模型，並且完成一套考慮溫度的統計型時序分析方法。所提出降低功率的方法利用功率延遲敏感度(power-delay sensitivity)作為最佳化的標準，並使用一個以切格子的(grid-based)方式來處理整個三維積體電路的結構。演算法中使用一個有效的觀念取代每次的統計型時序分析來增加運作效率。實驗的結果驗證了我們方法的有效性，並且指出在電路分析中考慮熱效應(thermal effect)是極重要的。The three-dimensional integrated circuits (3D ICs) have been viewed as an effective methodology to overcome the bottleneck caused by the long interconnects in the 2D IC. However, the higher temperature becomes a big challenge for 3D ICs. On-chip temperature can significantly affect the circuit performance so it is necessary to reduce the power dissipation in the circuit. Meanwhile, the process variations, which have a serious influence on the circuit design, are another important issue for the nanometer IC design. In this thesis, we present an approach to statistically minimize the total power consumption on the 3D ICs by using the dual supply voltage technology. By Karhunen-Loeve expansion, the random processes of physical parameters such as the channel length and the oxide thickness with spatial correlations are transformed to a set of uncorrelated random variables. Since the leakage power on the chip is a random process due to the process variations, we employ a statistical thermal simulation method to get the mean and variance of temperature distribution. To emphasize the impact of temperature, the leakage current and gate delay models are temperature related and we implement a thermal aware statistical timing analysis method. The proposed power reduction approach uses power-delay sensitivity as the optimization criterion, and a grid-based method for handling the whole structure of the 3D ICs. Instead of executing statistical timing analysis every time, a potent concept is used in the algorithm to achieve the run time efficiency. The experimental results demonstrate the effectiveness of our method and indicate that considering the thermal effect in the circuit simulation is imperative. URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009513616http://hdl.handle.net/11536/38465 Appears in Collections: Thesis

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