標題: 應用於晶片網路之低功率高可靠度傳輸架構基於自我更正節能編碼技術和自我校準電壓調整技巧
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme and Self-Calibrated Voltage Scaling Technique for Network-on-Chip
作者: 方瑋立
Wei-Li Fang
黃威
Wei Hwang
電子研究所
關鍵字: 低功率;晶片上傳輸;匯流排編碼技術;自我校準電壓調整技巧;晶片網路;Low power;On-chip Interconnect;Bus coding Scheme;Self-calibrated voltage scaling technique;Network-on-Chip
公開日期: 2007
摘要: 由於製程的迅速演進,晶片上的導線將會主導整體晶片效能。晶片網路設計被認為是有效整合多核心晶片系統的方法。在這篇論文中提出了一個結合匯流排編碼和錯誤更正碼的方法,這個方法由三重錯誤更正碼和節能匯流排編碼兩級組成。隨著更先進製程,三重錯誤更正碼將提供更可靠的更正機制,此外由於此方法可迅速編解碼,使之能有效地降低晶片網路交換結構中的位元數。節能匯流排編碼建立在三重匯流排模型上可以有效避免導線互相干擾,另外實現此編碼方法的電路也較簡單且有效。所提出的編碼法應用在NoC架構上不但使之容忍傳輸錯誤也實現了省能目的。以提出的編碼法為基礎,此篇論文另提出了一個可自我調整電壓的技巧,藉由兩級架構動態調整訊號電壓。測試干擾效應的偵錯級,藉由輸入最大干擾效應的測試信號來偵測錯誤。傳輸期的偵錯級,藉由兩次取樣資料檢查技巧來偵測錯誤,另外此級更提供了傳輸架構容忍時間變異的能力。根據偵錯的結果,自我調整電壓技巧可以降低信號電壓振幅,在達到省能的同時也能保證傳輸的可靠度。
Because of the shrinking of processing technology, the on-chip interconnect will dominate performance of hole chip in future. Network on Chip design have been considered an effective solution to integrate multiprocessor system. In this thesis, a joint bus and error correction coding, self-corrected green coding scheme is proposed. Self-corrected green coding scheme is constructed by two stages, which are triplication error correction coding stage and green bus coding stage. Triplication ECC provides a more reliable mechanism to advanced technologies. Moreover, in view of lower latency of decoder, it has rapid correction ability to reduce the physical transfer unit size of switch fabrics by self-corrected in bit level. The green bus coding employs more energy reduction by a joint triplication bus power model for crosstalk avoidance. In addition, the circuitry of green bus coding is more simple and effective. This approach not only makes the NoC applications tolerant against transient malfunctions, but also realizes energy efficiency. Based on proposed coding scheme, a self-calibrated voltage scaling technique is proposed, which adjusts the operation voltage by two stages. The crosstalk-aware test error detection stage detects the error by maximal aggressor fault test patterns in the testing mode. The run-time error detection stage detects errors by double sampling data checking technique; moreover, it provides the tolerance to timing variations. According to the error detections, the self-calibrated voltage scaling technique can reduce the voltage swing for energy reduction and guarantee the reliability at the same time.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511680
http://hdl.handle.net/11536/38200
Appears in Collections:Thesis


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