標題: 穩健次臨界靜態隨機存取記憶體與超低功率先進先出記憶體設計
Robust Subthreshold SRAM and Ultra-Low Power FIFO Memory Design
作者: 張牧天
Mu-Tien Chang
黃威
Wei Hwang
電子研究所
關鍵字: 次臨界靜態隨機存取記憶體;超低功率先進先出記憶體;subthreshold SRAM;ultra-low power FIFO memory
公開日期: 2007
摘要: 本論文提出高穩定性的超低功率靜態隨機存取記憶體及先進先出記憶體設計。超低電壓能夠有效地減少功率消耗,但靜態隨機存取記憶體也會因著電壓的下降而變得不穩健。本論文首先提出一個高穩定、全差分、單埠靜態隨機存取記憶體。利用自我補償及雜訊阻隔的機制,該記憶體能夠穩定地工作於超低電壓,而支援寫入的機制更可以提高於超低工作電壓時的寫入能力。利用UMC 90nm CMOS技術,模擬結果顯示,在0.2V工作電壓下,所提出的次臨界隨機存取記憶體與傳統的靜態隨機存取記憶體相比,有1.22倍的資料維持穩定性提升,2.09倍的讀取穩定性提升,及2.03倍的寫入能力提升。 除此之外,為了進一步減少漏電流,本論文利用自我電壓控制以及電源阻斷技術來降低先進先出記憶體陣列的漏電流;同時提出了一個高穩定性的雙臨界電壓、雙埠記憶體來增加可靠度並且減少功率消耗。模擬結果顯示,所提出的先進先出記憶體與傳統先進先出模組相比,具有多達94\%的功率削減。利用UMC 90nm CMOS技術,所提出的256行X16位元先進先出記憶體,於0.5V,5MHz讀取頻率,200kHz寫入頻率,有2.21uW的功率消耗。
Subthreshold SRAM and ultra-low power FIFO memory are indispensable to energy-constrained SoC. The stability of SRAM cell, however, has always been a major challenge to subthreshold SRAM design. This thesis proposes a robust, fully-differential subthreshold 10-transistor SRAM cell with auto-compensation. With the auto-compensation mechanism, the proposed cell exhibits better hold static noise margin (SNM). The cell structure also prevents storage nodes from bitline noise interference, thus improving read SNM. Better write ability is achieved by applying the write-assist technique. Based on UMC 90nm CMOS technology, simulation results show that, at 0.2V supply voltage, the proposed cell has 1.22X hold SNM improvement, 2.09X read SNM improvement, and 2.03X write margin improvement when compared to the conventional 6T SRAM cell. This thesis, in addition, also proposes a robust, ultra-low power asynchronous FIFO memory. With the self-adaptive power control and the complementary power gating technique, leakage power of the FIFO memory array is minimized. Further, the stability of the FIFO memory is improved under ultra-low supply voltage supply with the proposed dual-$V_T$ 7T SRAM cell. Simulation results indicate that the proposed scheme has up to 94\% power reduction over conventional designs. In this thesis, the proposed FIFO is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 2.21uW power consumption at 5MHz reading frequency and 200kHz writing frequency.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511630
http://hdl.handle.net/11536/38153
Appears in Collections:Thesis


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