Placement for Nanometer Low Dropout Regulators
|關鍵字:||類比電路;佈局自動化;擺放;Analog Circuits;Layout Automation;Placement|
As are motivated by Moores law, the circuit complexities for VLSI system are growing exponentially in the past decades. Digital designs are benefited from many powerful automatic design tools. However, the analog counterpart still demands huge engineering efforts and lengthy design period for technology migration. For a robust analog design may require several iterations to fulfill all the system specifications under process, voltage, and temperature variations, this scenario may become worse since many short channel effects are more pronounced as the devices step into the nanometer arena. In order to bridge the gap between analog and digital VLSI design capability, this work presents a framework for analog IP automatic design and layout synthesis. Employing low drop out regulator as a vehicle, the placer can generate a compact and regular layout a given circuit topology. In contrast to solving many overlooked circuit equations, the proposed complier is based on analog expert system concept and combines with simulated annealing. It can achieve the target goals for the first time right without time-consuming iterations. The layout synthesis part also automatically takes many design constraints for device matching and area optimization into considerations. To verify the performance of the placer, industrial cases are used to verify the correctness and quality of the resulting layout. The experimental results showed that our methodology can successfully apply to practical cases with rather compact and regular placement.
|Appears in Collections:||Thesis|
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