標題: H.264/AVC影像編碼系統在TI DSP系統平台上之實現與加速
Acceleration and Implementation of H.264/AVC Based Visual Communication System on TI DSP Platform
作者: 陳奕安
Chen Yi An
王聖智
Wang, Sheng-Jyh
電子研究所
關鍵字: H.264/AVC影像壓縮;數位訊號處理晶片;數位訊號處理晶片板;平行化;最佳化;德州儀器數位訊號處理晶片;參考架構5;H.264/AVC;DM642;MEX;Parallelization;Optimization;TI DSP;Reference framework 5
公開日期: 2008
摘要: 本論文中,我們針對了H264/AVC的影像壓縮規格,實現了一個即時影像傳輸系統。包含影像接收-壓縮-網路傳送端,以及網路接收-解壓縮-播放端,在一端送出經過H.264/AVC編碼技術壓縮過的資料,經過網際網路傳輸後可以被另一端收到並進行解碼。我們使用了多線程緒的執行方式,來達成此即時系統。針對DM642數位處理晶片,我們提出平行化的方法,並且也對具有多顆數位訊號處理晶片的MEX系統做平行化的處理。
In this thesis, we implement an H.264/AVC based real-time video communication system. The two ends of this system include video capturing/encoding/network-transmission and network-reception/ decoding/video-display. The H.264/AVC encoded data transmit from one end to the other end. The whole procedure is implemented in terms of multiple threads. To speed up the coding process, the optimization and parallelization of the DSP codes are performed with respect to the DM642 DSP chip and the multi-DSP board, MEX.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511608
http://hdl.handle.net/11536/38135
Appears in Collections:Thesis


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