標題: 90奈米互補式金氧半製程下之多功能輸入/輸出元件庫設計
Design of Configurable I/O Cell Library in 90-nm CMOS Process
作者: 陳世範
Shih-Fan Chen
柯明道
Ming-Dou Ker
電子研究所
關鍵字: 元件庫;輸入/輸出單元;靜電放電;互補式金氧半導體;90奈米;電壓迴轉率控制;cell library;I/O cell;ESD;CMOS;90nm;Slew-Rate Control
公開日期: 2008
摘要: 在積體電路(Integrated Circuits)設計中,元件庫(Cell Library)是不可或缺的一個重要部分,因為元件庫包含了組成積體電路的所有最基本單元。其中,輸入/輸出單元(Input/Output Cell, I/O Cell)連接積體電路與外界,並提供輸出驅動電流或接收輸入訊號的功能,亦保護積體電路免於遭受靜電放電(electrostatic discharge, ESD)損壞。然而,隨著互補式金氧半導體(Complementary Metal-Oxide-Semiconductor, CMOS)積體電路製程技術的演進,積體電路中的電晶體尺寸逐漸縮小,電路功能越來越多,操作速度也越來越快,元件庫勢必要提供更多不同功能的輸出入單元,以因應各種電路需求。此外,電晶體閘極氧化層的崩潰電壓隨著製程演進日益降低,造成積體電路產品的靜電放電耐受度下降。因此元件庫的設計在先進互補式金氧半製程中,存在更多的困難與挑戰。 本論文在90奈米互補式金氧半製程中,設計並驗證一套輸入/輸出元件庫,此多功能輸入/輸出元件庫包含多功能輸入/輸出單元(Configurable I/O Cell)、電源單元(Power Cell)、類比輸入/輸出單元(Analog I/O Cell)和電源切斷單元(Power Break Cell)。輸出單元內可以控制電流驅動能力,並可在三態(Tri-State)時選擇是否具有拉高(Pull Up)至高邏輯準位(Logic High)或拉低(Pull Down)至低邏輯準位(Logic Low)之功能。在輸入單元部分,可以選擇是否具有史密特觸發(Schmitt-Trigger)功能,以提升對輸入訊號的雜訊抵抗能力,這些功能皆由單一輸出入單元完成。此外,隨著瞬間輸出電流增加,接地電位彈跳現象(Ground Bounce)將越來越嚴重,使得電路可能發生功能錯誤的現象。本輸入/輸出單元亦提供一個具有電壓迴轉率控制(Slew-Rate Control)的多功能輸出入單元以抑制接地電位彈跳現象。靜電放電防護方面,本輸入/輸出元件庫提供了多組高效能靜電放電防護電路,以建構完整的全晶片(Whole-Chip)靜電放電防護。本論文以90奈米互補式金氧半製程設計並製作此輸入/輸出元件庫,實驗晶片的量測結果已成功驗證此輸入/輸出元件庫之所有功能,包含接收輸入訊號、傳送輸出訊號、電壓迴轉率控制與全晶片靜電放電防護。
The cell library plays an important role in integrated circuits (ICs), because it includes all of fundamental cells to construct the ICs. In the cell library, the input/output (I/O) cells provide the link between the ICs and outward. Thus, the I/O cells are used to provide the driving currents, to receive the input signals, and to protect the ICs against electrostatic discharge (ESD) damages. As the feature size of MOS transistors shrinks with the advance of complementary metal-oxide-semiconductor (CMOS) technology, the circuit functions become more complex and the operating frequency becomes higher. However, thinner gate-oxide decreases the ESD robustness of MOS transistors. Hence, there are more challenges and limits for the I/O cell library design in nanoscale CMOS technology. In this thesis, an I/O cell library is designed in 90-nm CMOS technology. The I/O cell library includes the configurable I/O cells, analog I/O cells, power cells, and power break cell. In the configurable I/O cell, the output stage is used to provide driving current. Besides, it can pull the I/O pad up to logic high or pull the I/O pad down to logic low under the tri-state. In input stage, a schmitt-trigger is realized and can be turned on to increase the noise margin of input signal. All of the aforementioned functions have been integrated in a single configurable I/O cell proposed in this thesis. Moreover, the ground bounce issue becomes more critical as the instantaneous driving current becomes larger. In the proposed I/O cell library, the slew-rate-control unit is realized in another configurable I/O cell to mitigate the ground bounce issue. In addition, several effective ESD protection circuits are designed in this I/O cell library to provide whole-chip ESD protection. The proposed I/O cell library has been fabricated in 90-nm CMOS process. Experimental results have successfully verified all of the functions provided in the I/O cell library, including receiving input signals, transmitting output signals, slew-rate control, and whole-chip ESD protection.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511593
http://hdl.handle.net/11536/38121
Appears in Collections:Thesis


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