標題: 以準分子雷射退火製作控制晶界位置之多閘極複晶矽薄膜電晶體之研究
Study on the Polycrystalline Silicon Thin-Film Transistors with Location-Controlled Grain Boundary and Multi-Gate Stucture Using Excimer Laser Annealing
作者: 李序恆
Syu-Heng Lee
鄭晃忠
Huang-Chung Cheng
電子研究所
關鍵字: 準分子雷射;複晶矽;薄膜電晶體;多閘極;excimer laser;poly-Si;thin film transistors;mutil-gate
公開日期: 2007
摘要: 近年來,低溫複晶矽薄膜電晶體成為顯示技術應用中的關鍵元件,由於其高載子遷移率的特性可以應用在系統面板(System on Panel, SOP)上。雖然透過傳統準分子電射退火方式可轉化非晶矽薄膜成為複晶矽,但此方法仍有些許缺點,如較狹窄的雷射製程條件、小晶粒與隨機分佈的晶粒邊界隨機分佈等等。在這篇論文裡,我們提出一種易於控制雷射結晶方式,並利用該雷射結晶方式配合多閘極結構來增進複晶矽薄膜電晶體的特性。 在第一部份,我們提出一種稱為氧化矽臺階式通道結晶法(Recessed-Channel with Oxide Step Method)之側向結晶方式,應用於製作可控制晶粒邊界位置之低溫複晶矽薄膜電晶體並加以探討,我們分析此種控制晶粒邊界位置技術之結晶機制分為山脊區與凹陷區之結晶:當雷射照射在凹陷區並使得完全熔融時,氧化矽側壁有較厚之未熔融矽薄膜作為晶種,晶粒便會在凹陷區作側向成長;當雷射照射在長度為2μm之山脊區時,由於山脊區中間部份比邊緣儲熱時間較久,故先有矽晶種產生且成長為小晶粒,阻擋由氧化矽側壁向山脊區中央側向成長之晶粒,我們把山脊區長度縮減為1.5 μm則可避免此現象;我們可以到均勻且方向一致的大型多晶矽晶粒分佈之複晶矽薄膜,因此可提升薄膜的均勻性與元件的效能。此外,我們利用掃描式電子顯微鏡、掃瞄原子力顯微鏡對控制晶粒邊界之複晶矽薄膜層分析,我們觀察到在谷區中有約1.5 μm長的人為控制晶粒,在山脊區有約0.75 μm長的人為控制晶粒。我們也利用此結晶方式製作出單一主要晶粒邊界的低溫複晶矽薄膜電晶體,並對其電特性加以研究。在無氫化過程處理下,其P型元件之場效載子移動率可達到168 cm2/V-s,其次臨界擺幅與汲極誘導體能障下降可達0.226 V/decade和310 mV。同時我們也比較製作元件於谷區與山脊區的各項電特性,在固定山脊區長度為2μm條件下,山脊區中間因有小型晶粒分佈,使得元件製作於山脊區之電特性較製作於谷區差,其製作於山脊區之元件的場效載子移動率為 99 cm2/V-s。 儘管單一主要晶粒邊界之複晶矽薄膜電晶體表現出良好的電特性,然而在元件通道中的單一主要晶粒邊界仍會對電特性產生影響。因此在第二部份,我們引入多閘極結構,研究避開單一晶粒邊界影響之電特性。在沒經過任何氫化處理過程下,P型元件之場效載子移動率更超過190 cm2/V-s。量測二十個元件的均勻性,場效載子移動率標準差小於30 cm2/V-s,臨界電壓的標準差小於0.78 V,次臨界擺幅之標準差0.113 V/decade。透過多閘極之結構,我們可以觀察到陡峭之次臨界擺幅,其可達0.164 V/decade。另外相較於傳統結晶方式之多閘極複晶矽薄膜電晶體,我們也獲得6倍以上之驅動電流。
In recent years, polycrystalline silicon (poly-Si) thin film transistors (TFTs) were the key devices in flat-panel display technology and System on a Panel (SOP) applications due to its high mobility. Although conventional excimer laser can transfer amorphous Si to polycrystalline Si in order to fabricate poly-Si TFTs. There were still some disadvantages such as narrow laser process window, random small grain and grain boundaries, and etc.. In this thesis, therefore, we proposed a method, which is so called Recessed-Channel with Oxide Step method, to control the grain growth and grain boundary. With the benefits of this crystallization method and multi-gate structure, high performance multi-gate poly-Si TFTs had been fabricated with no main grain boundary in the channel region. At the first part, single grain boundary (SGB) thin film transistors (TFTs) fabricated by excimer laser annealing were investigated. The crystallization mechanisms of valley region and ridge region of Recess-Channel with Oxide Step method were studied. A thick amorphous silicon region was formed in the sidewall of oxide step which acted as the seeds for the grain lateral growth during excimer laser irradiation. As the excimer energy density was controlled to completely melt the amorphous silicon thin film of valley region and partially melt the thick part in the sidewall of the oxide step. The lateral growth grain would be observed in the valley region. When laser irradiated the ridge region with channel length of 2 μm, the holding time of thermal energy of the edge of the ridge region was longer than that of the center of the ridge region. There were small grains in the middle of the ridge region, and the small grains obstructed the growth of the lateral grains from the sidewall to the center. We decreased the length of the ridge region to 1.5 μm, the phenomenon of grain obstruction would be eliminated. Therefore, the lateral growth grain starting from un-melt silicon seeds could extend along the opposite direction toward the complete melt valley region and ridge region. Thus, a uniform and large grain of polycrystalline silicon film would lead to improved device performance. According to the analysis of scanning electron microscope (SEM) and atomic force microscope (AFM), large longitudinal grains were observed to be about 1.5 μm in valley region and about 0.75 μm in ridge region. The electrical characteristics of single grain boundary TFTs fabricated by Recessed-Channel with Oxide Step TFTs were also investigated. High performance p-type SGB-TFTs with field-effect mobility reaching 168 cm2/V-s had been fabricated without any hydrogenation treatment. The subtheshold swing and drain-induced-barrier-lowing (DIBL) of SGB-TFTs were 0.226 V/decade and 310 mV respectively. In addition, the electrical characteristics of devices located on the valley region and ridge region were studied. While the length of ridge region was 2μm, there was a small grain region in the middle of ridge region. Because the crystalline of ridge region of poly-Si thin film was defective, the electrical characteristics of devices located on ridge region were poorer than that of devices located on valley region. The field-effect mobility of devices located on ridge region was 99 cm2/V-s. Although SGB-TFTs exhibited high performance, the electrical characteristics of SGB-TFTs were affected by the single main grain boundary located in device channel. Hence, we introduced the multi-gate (MG) structure to eliminate the single grain boundary effect and investigated the electrical characteristics of multi-gate TFTs in order to avoid the single main grain boundary in the channel. High performance p-type MG-TFTs with field-effect mobility exceeding 190 cm2/V-s had been fabricated without any hydrogenation treatment. The characteristics of twenty MG-TFTs devices were taken into discussion. The standard deviation of equivalent field-effect mobility was smaller than 30 cm2/V-s and the standard deviation of Vth was smaller than 0.78 V, while that of subthreshold swing was smaller than 0.113 V/decade. By means of multi-gate structure, the steeper subthreshold swing reaching 0.164V/decade was obtained. Furthermore, MG-TFTs provided 6 times higher driving current than conventional TFTs.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511585
http://hdl.handle.net/11536/38112
Appears in Collections:Thesis


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