標題: 多閘極氮化鈦奈米晶粒非揮發性記憶體之研究
A Study on the Multi-gate TiN Nano-crystal Non-volatile Memory
作者: 羅正愷
崔秉鉞
電子研究所
關鍵字: 記憶體;奈米晶粒;氮化鈦;多閘極;非揮發性;memory;nano-crystal;TiN;multi-gate;non-volatile;flash
公開日期: 2007
摘要: 在本論文中,我們提出一個在SOI晶片上的N型通道氮化鈦 (TiN) 奈米晶粒非揮發性記憶體的捕陷電荷層設計。採用P型参雜的多晶矽閘極和高K值的阻隔介電層分別是為了降低抹除時的背向注入漏電流與較低的操作電壓。氮化鈦奈米晶粒的形成是利用將原子層沉積裝置多次循環層積所得的氮化矽與氧化鋁層退火所得到的。此多閘極氮化鈦奈米晶粒非揮發性記憶體元件的物理通道長度為80奈米而其物理通道寬度為50奈米。氮化鈦奈米晶粒的大小約為1到2奈米。我們將會探討不同製程條件如不同的氮化鈦沉積厚度、不同的阻隔介電層厚度與不同退火時間對記憶體特性的影響。 可以發現擁有比較厚的氮化鈦沉積厚度的元件其記憶窗口明顯較大。此記憶體元件的寫入/抹除速率表現普通而且沒有明顯的飽和現象。另外,此記憶體元件在外插到十年線後仍擁有良好的儲存資料持久性而且在104次寫入/抹除之後幾乎沒有性能退化。微小的讀取干擾與寫入干擾說明了此氮化鈦奈米晶粒非揮發性記憶體適合運用在NAND 型的非揮發性記憶體上。 最後,我們提出一種新穎的記憶體操作方法。此種新穎的記憶體操作方法係利用在BBHH與CHE操作之後感測元件關閉狀態的漏電流的方式來完成資料的讀取。利用此方法,其記憶窗口在 106秒後縮小幾乎可被忽略且元件也可以操作在低電壓的範圍。此新穎的記憶體操作方式的機制與造成其突出的儲存資料持久性的原因目前尚未充分了解。我們相信其有深入研究的價值。
In this thesis, we proposed a trapping layer engineered n-channel multi-gate TiN nano-crystal non-volatile memories on SOI wafer. P+ poly-Si gate and Al2O3 high-K blocking dielectric are used to suppress electron back tunneling current during erase operation and to reduce operation voltage, respectively. TiN nano-crystals are formed by annealing the ALD-deposited TiN/Al2O3 nano-laminate. Small geometry multi-gate TiN nano-crystal non-volatile memory cell with physical gate length of 80nm and physical fin width of 50nm is fabricated. The TiN nano-crystals have diameter of 1~2nm. Memory performance of the cells with different thicknesses of TiN layer, blocking layer, and with different anneal time are investigated. It can be found that device using thicker TiN nano-laminate has much larger memory window than the others. The memory exhibits acceptable program and erase speed and little Vt shift saturation. Good 10-year extrapolated charge retention and high endurance after 104 P/E cycles are also exhibited. The small read and gate disturbance characteristics show that the TiN nano-crystal memory cell adapts to the application of NAND type flash memory. Finally, we present a novel memory operation scheme by sensing the level of off-region current after ban-to-band hot hole programming. Negligible memory window narrowing after 106 seconds and low operation voltage have been demonstrated. The mechanism of this operation scheme and outstanding retention performance is not clear at this moment and is worthy to be investigated.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511525
http://hdl.handle.net/11536/38067
Appears in Collections:Thesis


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