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dc.contributor.author陳膺任en_US
dc.contributor.authorYing Jen Chenen_US
dc.contributor.author荊鳳德en_US
dc.contributor.authorAlbert Chinen_US
dc.date.accessioned2014-12-12T01:13:34Z-
dc.date.available2014-12-12T01:13:34Z-
dc.date.issued2007en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009511522en_US
dc.identifier.urihttp://hdl.handle.net/11536/38064-
dc.description.abstract本論文展示了一種以非對稱輕摻雜汲極金氧半體電晶體作為功率單元的2.4GHz 射頻功率放大器架構,該放大器可完全以TSMC 0.18um的CMOS一般製程環境來實現。這個設計可以穩定的操作在2.5V ~ 2.75V,而不需使用串接電路。較高的操作電壓使得電路有優越的功率特性,根據晶片實際量測的結果,2.5V 工作電壓條件下,功率增益達20dB,功率增加效率(PAE)達30%,2.75V的工作電壓條件下,輸出功率P1dB可達21.5dBm 飽和輸出功率可達23.2dBm,並且測得W-CDMA π/4 QPSK調變下,鄰近通道功率比在15dBm的輸出功率為-41dBc,與大約36dBm的輸出三階互調截點(OIP3)。zh_TW
dc.description.abstractThis thesis presents a 2.4 GHz RF CMOS power amplifier based on two stages amplifiers topology with asymmetric-lightly-doped-drain (LDD) CMOS power cell which is fully embedded in the conventional foundry logic process with only one additional mask but without extra process step. The power amplifier can achieved higher output power and higher power-added efficiency (PAE) and novel linearity. The simulation result demonstrated 20dB power gain, and 30% PAE with 2.5V supply voltage, 21.5dBm at 1-dB compression point (P1dB), 23.2dBm saturate output power, -41dBc ACPR at 15dBm output power point with standard W-CDMA π/4 QPSK modulation , and ~36dBm OIP3 with 2.75V supply voltage.en_US
dc.language.isoen_USen_US
dc.subject功率放大器zh_TW
dc.subject互補式金屬氧化半導體zh_TW
dc.subjectCMOSen_US
dc.subjectpower amplifieren_US
dc.subjectPAen_US
dc.subjectLDDen_US
dc.subjectClass ABen_US
dc.subject2.4GHzen_US
dc.title非對稱輕摻雜汲極金屬氧化半導體電晶體應用於2.4GHz 射頻功率放大器zh_TW
dc.titleA 2.4GHz RF CMOS Power Amplifier Using High Breakdown Voltage Asymmetric-LDD MOS Transistorsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis


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