標題: 複晶矽薄膜電晶體的充放電機制用於記憶應用之研究
A Study of Trapping/De-trapping Mechanisms in Poly-Si Thin Film Transistors for Memory Applications
作者: 洪政雄
Cheng-Hsiung Hung
林鴻志
黃調元
Horng-Chih Lin
Tiao-Yuan Huang
電子研究所
關鍵字: 遲滯現象;薄膜電晶體;奈米線;複晶矽薄膜;複晶矽鍺薄膜;hysteresis;thin film transistor;nanowire;polycrystalline silicon film;polycrystalline SixGe1-x film
公開日期: 2007
摘要: 在本論文研究中,我們在複晶矽薄膜電晶體傳導特性中觀察到一種有趣的遲滯(hysteresis)現象,並對此進行深入的探討。為了清楚的瞭解其發生的起因,本研究針對可能調控此現象的參數,包括:通道厚度、通道長度、通道寬度、電漿處理及溫度等,設計相關的實驗以解析其影響。根據實驗的結果,我們提出一物理模型,利用複晶矽薄膜電晶體中晶界充放電機制,說明在特定條件下造成此種遲滯現象的原因與過程。此外,本論文也探討不同材料與元件組態對於遲滯現象的影響。我們的研究也同時評估,複晶矽元件之遲滯特性對於將來運用於記憶體應用之可行性。
A new hysteresis phenomenon presenting in the current-voltage characteristics of poly-Si thin-film transistors (TFTs) was discovered, for the first time, in our experiments. Mechanisms reported in previous literatures fail to explain the finding. To clearly understand the root cause of the hysteresis, we examine several factors that might affect the phenomenon, including channel thickness, channel length, channel width, post-metal treatment, and temperature, etc. From the results, we propose a physical model, based on the trapping/detrapping events occurring in the grain boundaries of poly-Si thin film transistors (TFTs), to reasonably explain the hysteresis behavior of poly-Si TFTs. Besides, we also investigate the effects of Ge incorporation in the channel and structural factors on the hysteresis characteristics. Our findings indicate the potentiality of the poly-Si devices for future memory applications.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009511518
http://hdl.handle.net/11536/38060
Appears in Collections:Thesis