ESD Impacts on Low Dropout Voltage Circuit
The thesis proposes a low-dropout (LDO) regulator with ESD Impacts. Thus, the content of this thesis contains two parts. The first part discusses the design of a low-dropout regulator. With the exponentially increasing of portable battery-powered electronic equipments, such as mobile phones, digital cameras and so on, power management has becoming more and more important and popular. The design of low dropout regulators is widely used in power management since it has a better load transient response, less output noise, and few off-chip components compared to the design of switch-mode regulators. Stability is an important issue in the design of LDO linear regulators. In the conventional architecture, the key factors affecting the system stability are the wide load current range and the value of the output capacitor. Therefore, there exist many proposed compensation techniques to stabilize and improve the whole system. According to the type of output capacitor, LDO regulators can be simply classified into two groups: LDOs with off-chip or on-chip output capacitor. These LDO linear regulators with off-chip capacitor need a large capacitance at output node to generate a dominant pole at low frequency to achieve the stability. They are mostly used for supplying the system with the characteristic of low quiescent current at light loads owing to the current efficient buffer used in the LDOs. The other LDO regulators use an on-chip small output capacitor based on the Miller-compensated technique. Thus, the capacitor can be integrated into the chip, which has the advantage of the saving the footprint area. This type of capacitor-free LDOs is well suited as a stable dc voltage supply for portable electronic devices. The second part of this thesis discusses how ESD impacts the low-dropout regulators. In some situation, the latent damage of electrostatic discharge in a power MOSFET can't easily find out immediately. Eventually, in order to make sure a good reliability and long lifetime of power MOSFETs, the ESD protection circuit design is needed to prevent ESD damages in a power MOSFET design. This thesis provides the reliability engineers of integrated circuit a most important concept of ESD design of power IC. The improvement of the ESD will enhance the reliability of integrated circuit in power IC designs.
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