Title: 1 x 128紅外線偵測器線性陣列之互補式金氧半讀出積體電路設計與分析
THE DESIGN AND ANALYSIS OF CMOS READOUT INTEGRATED CIRCUIT FOR 1x128 LINEAR INFRARED PHOTODETECTOR ARRAY
Authors: 鄭人文
Ren-Wen Cheng
吳重雨
Chung-Yu Wu
電機學院IC設計產業專班
Keywords: 讀出;紅外線;線性;偵測器;READOUT;INFRARED;LINEAR;PHOTODETECTOR
Issue Date: 2007
Abstract: 本論文提出並分析新型互補式金氧半(CMOS)電流讀出電路設計技巧製作運用在紅外線偵測器線性陣列光訊號讀出之積體電路晶片,用於讀出中華電信研究所所開發出的紅外線感應器線性陣列。讀出電路為紅外線影像偵測系統中線性偵測器陣列輸出訊號至後級訊號處理之間的重要介面電路。本論文提出了新型電流之讀出電路架構,並以互補式金氧半製程技術完成電路的設計與模擬。 利用『緩衝式直接輸入』(Buffered Direct Injection)讀出架構,可以改進傳統『直接輸入』(Direct Injection)的問題與缺點。此前級訊號處理功能(on-FPA signal processing)可以提高讀出電路的效能並降低後級電路雜訊之影響。四種可選擇的積分電容和可獨立控制積分時間的功能更可增加光電流範圍。改良後的雙重三角取樣(Double Delta Sampling)電路除了可以減少固定樣式雜訊(fixed pattern noise)、時脈回饋雜訊、通道電荷注入和共模雜訊,還可以改善線性度和增加輸出電壓的擺幅。1 x 128讀出晶片使用0.35 μm 2P4M N-well互補式金氧半技術設計並完成晶片研製,在298K溫度下及3.3 V工作電壓,其量測結果成功驗證了讀出晶片的效能。晶片尺寸7.4mmx1.6mm、輸出線性度為99.73%、最大輸出擺幅為1.6V、最大讀出速度為10MHz、最大畫面速率為30k frames/sec(4MHz讀出速率)、可調積分37.42us到0.935us (畫面速率為26k frames/sec)、功率消耗為14.5 mW。此高效能讀出電路具有高注入效率(injection efficiency)、高電荷容量(storage capacity)、高可調積分範圍、低雜訊等優點,可適用於大範圍亮度與高對比影像讀出的運用。 我們深信,吾人所提出之互補式金氧半讀出電路架構以及其設計技術已為紅外線影像系統之讀出處理電路設計提供一個新方向。爾後,相關的研究發展與實際應用於不同影像系統包括可見光與紅外線將持續進行。
In this thesis, a CMOS readout structure is proposed, developed, and applied to the implementation of photon signal readout integrated circuit for 1x128 linear InGaAs infrared photodetector array. The silicon readout circuit is an important interface circuit of detector array and signal processing stage in the IR image system. To achieve high performance readout and fit the working characteristic of IR detector material, a CMOS readout structure has been developed and fabricated. The functions and superior readout performance of the proposed CMOS readout structure have been verified by experimental measurement under 298K environment or simulations. By using the buffered direct injection (BDI) circuit, it can improve the performance and problem of the conventional Direct Injection (DI). The on-FPA signal processing capability of BDI circuit at front stage can reduce the noise effect of downstream circuit and improve the readout performance. The selectable integration capacitors and independent integration time control can enhance the optical current range. Moreover, the improved double delta sampling (DDS) circuit is used to not only suppress fixed pattern noise, clock feedthrough noise, channel charge injection but also common mode noise. An experimental 1 x 128 readout chip has been designed and fabricated by using 0.35 μm 2P4M N-well CMOS technology. The measurement results of the fabricated readout chip under 298K and 3.3 V supply voltage have successfully verified both readout function and performance. The size of the chip is 7.4mmx1.6mm. The linearity performance of the readout chip is better than 99.73% and the maximum output swing is 1.6V. The maximum readout speed is 10 MHz. The maximum frame rate at 4 MHz readout speed is 30k frames/sec. The integration time tunable range at 26k/s frame rate is from 37.42us to 0.935us. The total active chip power is below 14.5 mW at 298K. It is shown that a high-performance readout interface circuit for linear IR FPA with high injection efficiency, high charge sensitivity, large storage capacity, wide integration time tunable range and low noise is realized. These advantageous traits make the readout circuit suitable for the various applications. It is believed that the proposed CMOS readout circuit and the associated design methodology offer new design scope and future feasibility for new-generation readout ICs of infrared detector array. Further improvement on circuit performance and practical applications in various image system including visible and thermal image readout will be explored and developed in the future.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009495501
http://hdl.handle.net/11536/37979
Appears in Collections:Thesis


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