標題: 低溫複晶矽面板上之靜電放電耐受度研究
Investigation on Electrostatic Discharge (ESD) Robustness of Low Temperature Poly-Silicon (LTPS) Devices and Panels
作者: 莊介堯
Jie-Yao Chuang
柯明道
Ming-Dou Ker
電機學院微電子奈米科技產業專班
關鍵字: 靜電放電;低溫複晶矽;面板;Electrostatic Discharge;ESD;Low Temperature Poly-Silicon;LTPS
公開日期: 2007
摘要: 低溫複晶矽(low temperature poly-silicon, LTPS)薄膜電晶體(thin-film transistors, TFT)已被視為一種材料廣泛地研究於可攜帶式系統產品中,例如數位相機、行動電話、個人數位助理(PDA) 、筆記型電腦等等,這是由於低溫複晶矽薄膜電晶體的電子遷移率(electron mobility)約是傳統非晶矽(amorphous silicon)薄膜電晶體的百倍大。此外,低溫複晶矽技術可藉由將驅動電路整合於顯示器之週邊區域來達到輕薄、巧小且高解析度的顯示器。這樣的技術也將越來越適合於系統面板(system-on-panel/system-on-glass)應用之實現。 靜電放電(electrostatic discharge, ESD)在積體電路(integrated circuits, ICs)中是一個產品可靠度上的重要問題。當靜電放電發生於平面顯示器上時,常會造成產品生產良率的降低,所以如何防制靜電放電的發生,在平面顯示器的生產上更是一重要課題。 基於此,本論文詳細研究了在3□m低溫複晶矽薄膜製程下之靜電放電防護元件,並藉由在元件上變化不同的佈局參數,使用傳統的傳輸線脈衝(transmission line pulsing, TLP)產生系統和長脈衝-傳輸線脈衝系統(long-pulse transmission line pulsing system, LP-TLP)觀測元件在靜電轟擊下之電性特徵。本論文利用傳統型傳輸線脈衝系統及長脈衝-傳輸線脈衝系統量測到之待測薄膜元件之二次崩潰特性(secondary breakdown characteristic)點,來說明及探討元件佈局結構之靜電耐受力的影響,並憑藉量測不同參數和佈局尺寸的薄膜元件,可歸納出應用於液晶面板上的靜電放電防護設計之最佳化方式。 在全系統面板應用電路設計組裝中,因隨著全面板的生產過程之各模組的組裝,待組裝物、設備或是人員之間所產生的面板上靜電放電,以致於越來越嚴重良率下降問題;故本論文藉由利用於觀測面板上之靜電放電實際事件,來進一步分析電路元件遭受人體放電模式(Human Body Model, HBM),機器放電模式(Machine Model, MM)及模組儲存電荷模式(Charged Device Model, CDM) 之元件故障點分析。
Low temperature poly-silicon (LTPS) thin-film transistors (TFTs) have been widely investigated as a material for portable systems, such as digital camera, mobile phone, personal digital assistants (PDAs), notebook, and so on, because the electron mobility of LTPS TFTs is about 100 times larger than that of the conventional amorphous silicon TFTs. Furthermore, LTPS technology can achieve slim, compact, and high-resolution display by integrating the driving circuits on peripheral area of display. This technology will also become more suitable for realization of system-on-panel/system-on-glass (SoP/SoG) applications. The electrostatic discharge (ESD) is one of the major reliability concerns in integrated circuits (ICs) and the most critical issue on the flat display panel to reduce the production yield. In order to design high performance ESD protection device and realize the secondary breakdown characteristic of ESD protection devices in 3-μm LTPS technology, the turn-on characteristics of those devices must be measured and analyzed by using the long-pulse transmission line pulsing (LP-TLP) system and traditional 100-ns transmission line pulsing (TLP) system in this thesis. From the investigation of layout dependence on ESD protection devices with finger-type layout, the turn-on mechanisms of ESD protection devices can be clearly understood to optimize the layout rules for the device dimensions, the layout style, and the layout spacing of those devices. More ESD problems on panel are growing importance due to many industrial cases where such discharges have resulted in numerous device failures of electrostatic origin for the assemblies/modules. The goal of this thesis is to analyze and explain the integrated circuit of whole-panel under LTPS process the effects that are seen on display panel when they are subjected to the charged device model (CDM) versus human body model (HBM) and machine model (MM) ESD events
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009494506
http://hdl.handle.net/11536/37961
Appears in Collections:Thesis


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