標題: EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS
作者: HWANG, JS
WU, CY
交大名義發表
電子工程學系及電子研究所
National Chiao Tung University
Department of Electronics Engineering and Institute of Electronics
關鍵字: OPTIMIZATION;LOGIC
公開日期: 1-May-1991
摘要: Two techniques are proposed which enhance the optimisation efficiency of CMOS combinational logic circuits. One uses transition times (rise and fall times) of each gate as variables of the optimisation process. The other technique uses the optimal characteristic waveform synthesising method (OCWSM) to obtain the initial guess for the optimisation process. The optimisation process, with these two techniques, can perform sizing and optimisation for circuits with a smaller fixed-delay specification than other sizing and optimisation algorithms. The circuits sized using the proposed algorithm have shown a smaller power dissipation, especially when the delay specification is small. The CPU time consumed is reasonable. High-speed low-power circuits are thus more realisable using the proposed algorithm.
URI: http://hdl.handle.net/11536/3795
ISSN: 0143-7062
期刊: IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES
Volume: 138
Issue: 3
起始頁: 154
結束頁: 164
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  1. A1991FL50700007.pdf