標題: LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI
作者: WU, CY
CHENG, KH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-九月-1991
摘要: A new CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate, and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results have verified the high speed and race-free performance of the proposed LCDL.
URI: http://dx.doi.org/10.1109/4.84952
http://hdl.handle.net/11536/3692
ISSN: 0018-9200
DOI: 10.1109/4.84952
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 26
Issue: 9
起始頁: 1324
結束頁: 1328
顯示於類別:期刊論文


文件中的檔案:

  1. A1991GC00300019.pdf