標題: Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure
作者: Chen, Shih-Ching
Chang, Ting-Chang
Liu, Po-Tsun
Wu, Yung-Chun
Lin, Po-Shun
Chen, Shih-Cheng
Chin, Jing-Yi
Sze, S. M.
Chang, Chun-Yen
Lien, Chen-Hsin
電子工程學系及電子研究所
光電工程學系
Department of Electronics Engineering and Institute of Electronics
Department of Photonics
關鍵字: poly-Si;SONOS;nanowire;nonvolatile memory;thin film transistor (TFT)
公開日期: 15-Dec-2007
摘要: In this work, we study a polycrystalline silicon thin-film transistor (poly-Si TFT) combined with a silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire channels structure for the applications of transistor and nonvolatile memory. The proposed device named with NW SONOS-TFT has superior electrical characteristics of transistor and also can exhibit high program/erase (P/E) efficiency under adequate bias operation. The V-th decreases from 2.45 V to 1.76 V and subthreshold swing reduces from 0.57 V/decade to 0.42 V/decade. The programming V-th shift is improved from 2.2 V to 3.3 V at 14 V for 1 s and the erasing V-th shift is improved from -0.3 V to -1.3 V at -14 V for 1 s. The dramatic improvement can be attributed to the tri-gate structure and corner effect. In addition, the memory device has a promising data retention behavior at 85 degrees C and a 0.8 V memory window after 5 x 10(3) P/E cycles operations. Hence, the NW SONOS-TFT is suitable for application in the future system-on-panel display. (C) 2007 Elsevier B.V. All rights reserved.
URI: http://dx.doi.org/10.1016/j.surfcoat.2007.07.111
http://hdl.handle.net/11536/3652
ISSN: 0257-8972
DOI: 10.1016/j.surfcoat.2007.07.111
期刊: SURFACE & COATINGS TECHNOLOGY
Volume: 202
Issue: 4-7
起始頁: 1287
結束頁: 1291
Appears in Collections:Conferences Paper


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