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dc.contributor.authorCHENG, MHen_US
dc.contributor.authorHUANG, TCen_US
dc.date.accessioned2014-12-08T15:05:05Z-
dc.date.available2014-12-08T15:05:05Z-
dc.date.issued1991-12-01en_US
dc.identifier.issn0956-3768en_US
dc.identifier.urihttp://hdl.handle.net/11536/3615-
dc.description.abstractThe paper presents two switched-capacitor circuits with modest complexity to implement a pipelined logarithmic digital-analogue convertor (LDAC) and logarithmic analogue-digital convertor (LADC), respectively, which spend only one clock time per conversion. In addition, the effect of the capacitor-ratio mismatch on the conversion errors of the convertor circuits is discussed. Hence, from the available maximum capacitor-ratio value and mismatch of the present integrated circuit (IC) technology, the feasible bit length of the pipelined LDAC and LADC can be computed.en_US
dc.language.isoen_USen_US
dc.subjectCONVERTERSen_US
dc.subjectCIRCUIT THEORY AND DESIGNen_US
dc.titleSWITCHED-CAPACITOR PIPELINED LOGARITHMIC A/D AND D/A CONVERTERSen_US
dc.typeArticleen_US
dc.identifier.journalIEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMSen_US
dc.citation.volume138en_US
dc.citation.issue6en_US
dc.citation.spage714en_US
dc.citation.epage716en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:A1991GT22800013-
dc.citation.woscount0-
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