標題: Identifying invalid states for sequential circuit test generation
作者: Liang, HC
Lee, CL
Chen, JE
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: invalid states;sequential test generation;VLSI testing
公開日期: 1-九月-1997
摘要: For sequential circuit test pattern generation incorporating backward justification, we need to justify the values on pip-pops to activate and propagate fault effects, This takes much time when the values to be justified on flip-flops appear to be invalid states, Hence, it is desirable to know invalid states, either dynamically during the justification process or statically before proceeding to test generation. This paper proposes algorithms to identify, before test generation, invalid states for sequential circuits without reset states, The first algorithm explores all valid states from an unknown initial state to search the complete set of invalid states, The second algorithm finds the complete set of invalid states from searching the reachable states for each state, The third algorithm searches the invalid states which are required for test generation to help stop justification early by analyzing dependency among flip-flops to simulate each partial circuit, Experimental results on ISCAS benchmark circuits show that the algorithms can identify invalid states in short time. The obtained invalid states were also used in test generation, and it was shown that they improved test generation significantly in test generation time, fault coverage, and detection efficiency, especially for larger circuits and for those that were difficult to generate.
URI: http://dx.doi.org/10.1109/43.658570
http://hdl.handle.net/11536/357
ISSN: 0278-0070
DOI: 10.1109/43.658570
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 16
Issue: 9
起始頁: 1025
結束頁: 1033
顯示於類別:期刊論文


文件中的檔案:

  1. 000072350200009.pdf