標題: BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATE
作者: LEE, CL
JEN, CW
交大名義發表
電控工程研究所
National Chiao Tung University
Institute of Electrical and Control Engineering
關鍵字: FILTERS AND FILTERING;BOOLEAN ALGEBRA
公開日期: 1-Feb-1992
摘要: There are arithmetic problems for the hardware realisation of bit-level median filtering algorithms. A design of a majority gate which is composed of output-wired inverters is proposed. The area and time complexities are better than the digital and analogue designs now available. This circuit is applied to a median filter design which is based on majority selection, the computation problems are thus avoided. It is a bit-sliced architecture with constant cycle time. Window shapes can be arbitrarily changed through mask-and-set modules. A median filtering system for two-dimensional image processing is presented. A binary majority gate is also an essential element in decision-making circuitry which is applied in fault-tolerant computing systems, artificial neural networks or related applications.
URI: http://hdl.handle.net/11536/3539
ISSN: 0956-3768
期刊: IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS
Volume: 139
Issue: 1
起始頁: 63
結束頁: 71
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  1. A1992HD51500012.pdf