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dc.contributor.authorHSIEH, SFen_US
dc.contributor.authorLIU, KJRen_US
dc.contributor.authorYAO, Ken_US
dc.date.accessioned2014-12-08T15:04:53Z-
dc.date.available2014-12-08T15:04:53Z-
dc.date.issued1992-06-01en_US
dc.identifier.issn1057-7130en_US
dc.identifier.urihttp://dx.doi.org/10.1109/82.145296en_US
dc.identifier.urihttp://hdl.handle.net/11536/3398-
dc.description.abstractWe propose a dual-state systolic structure to perform joint up/down-dating operations encountered in windowed recursive least-squares (RLS) estimation problems. It is based on successively performing Givens rotations for updating and hyperbolic rotations for downdating. Due to data independency, a series of Givens and hyperbolic rotations can be interleaved and parallel processing can be achieved by alternatively performing updating and downdating both in time and space. This flip-flop nature of up/down-dating characterizes the feature of the dual-state systolic triarray. Efficient implementation on the evaluation of optimal residuals is also considered. This systolic architecture is promising for the VLSI implementation of fixed size sliding-window recursive least-squares estimations.en_US
dc.language.isoen_USen_US
dc.titleDUAL-STATE SYSTOLIC ARCHITECTURES FOR UP DOWNDATING RLS ADAPTIVE FILTERINGen_US
dc.typeNoteen_US
dc.identifier.doi10.1109/82.145296en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSINGen_US
dc.citation.volume39en_US
dc.citation.issue6en_US
dc.citation.spage382en_US
dc.citation.epage385en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:A1992JD57100007-
dc.citation.woscount3-
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