標題: DESIGNING A COMPLEMENTARY DESIGN RULE CHECKER BASED ON A BINARY BALANCED QUAD LIST QUAD TREE
作者: HSIAO, PY
YAN, JT
交大名義發表
資訊工程學系
National Chiao Tung University
Department of Computer Science
關鍵字: COMPUTER-AIDED DESIGN;DESIGN RULE CHECKER;VLSI LAYOUT;BALANCED QUAD TREE
公開日期: 1-七月-1992
摘要: An efficient real time VLSI-CAD tool, the complementary design rule checker (CDRC), composed of one interactive phase and one batch phase is presented. It is a general geometrical design rule model which checks some of the layout constraints in the interative phase and the other constraints in the batch phase. Those classified constraints are disjointed, and each one of them should be checked only once either during the interactive or batch phase. This system and the embedded layout editor are designed on the basis of the binary balanced quad list quad tree (BBQLQT) and its region query functions. The BBQLQT is more efficient than the most recently published spatial data structure, the Weyten's quad list quad tree. One day, provided that the BBQLQT has being further improved, the performance of our system will be promoted without giving more additional design effort. This system is therefore proven to be fully modularised and independent of any of the other spatial data structures.
URI: http://hdl.handle.net/11536/3372
ISSN: 0143-7062
期刊: IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES
Volume: 139
Issue: 4
起始頁: 311
結束頁: 322
顯示於類別:期刊論文


文件中的檔案:

  1. A1992JJ05100003.pdf