標題: Low power parallel Huffman decoding
作者: Lin, CH
Jen, CW
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 5-二月-1998
摘要: A low power design technique for a parallel Huffman decoder is presented. According to the length of the incoming Huffman codeword, the proposed strategy makes the barrel shifter in the parallel Huffman decoder turn off the unnecessary shifting bits to reduce power dissipation. The result of a SPICE simulation indicates that up to 50 percent power reduction in the barrel shifter may be achieved with the proposed technique.
URI: http://hdl.handle.net/11536/32794
ISSN: 0013-5194
期刊: ELECTRONICS LETTERS
Volume: 34
Issue: 3
起始頁: 240
結束頁: 241
顯示於類別:期刊論文


文件中的檔案:

  1. 000072152200011.pdf