標題: Static power analysis for power-driven synthesis
作者: Yuan, SY
Chen, KH
Jou, JY
Kuo, SY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: probabilistic method;simulation-based method;symbolic simulator
公開日期: 1-三月-1998
摘要: A new static power analysis method for CMOS combinational circuits is presented. This approach integrates the simulation-based method and the plobabilistic method, and can establish the relationships between the primary inputs and the internal nodes in the circuit. Based on the relationships, our approach can also indicate which internal node or input sequence consumes the most power. It is thus suitable for performing power estimation in the synthesis environment for power optimisation. To the best of our knowledge, this is the first attempt to develop a systematic way to symbolically represent the relationships between the primary inputs and the power consumption at every internal node of a circuit. Furthermore, by using the existing piecewise linear delay model, as well as the proposed algorithm, this novel method is also very accurate and efficient. For a set of benchmark circuits, the experimental results show that the power estimated by our technique is within 5% error as compared with that by the exact SPICE simulation, while the execution speed is more than four orders of magnitude speed is faster.
URI: http://hdl.handle.net/11536/32763
ISSN: 1350-2387
期刊: IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES
Volume: 145
Issue: 2
起始頁: 89
結束頁: 95
顯示於類別:期刊論文


文件中的檔案:

  1. 000073069600003.pdf