標題: Sensitisable-path-oriented clustered voltage scaling technique for low power
作者: Jou, JY
Chou, DS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: clustered voltage scaling technique;benchmark circuits
公開日期: 1-七月-1998
摘要: Because the average power consumption of CMOS digital circuits is consumption proportional voltage, a clustered voltage scaling (CVS) technique has previously been proposed to reduce power without sacrificing the circuit performance. In this paper the authors propose a path-oriented CVS algorithm, which can take the false paths into account. Extensive experiments are conducted on ISCAS85 benchmark circuits. These experiments show that many more gates can be voltage scaled down in comparison with the original CVS technique. An additional 22% power reduction ratio over that of the original CVS technique is achieved.
URI: http://hdl.handle.net/11536/32538
ISSN: 1350-2387
期刊: IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES
Volume: 145
Issue: 4
起始頁: 301
結束頁: 307
顯示於類別:期刊論文


文件中的檔案:

  1. 000075323100008.pdf