標題: A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up
作者: Chen, MJ
Lee, HS
Chen, JH
Hou, CS
Lin, CS
Jou, YN
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-八月-1998
摘要: A new physical model concerning the holding points for latch-up in epitaxial CMOS structures is established by combining the lateral p-i-n high level injection and the vertical BJT base push-out formula. The model matches adequately the correlation between holding voltage and holding current extensively measured from different combinations of temperatures, epitaxial layer thicknesses, and anode-to-cathode spacings, This is also the case for the two-dimensional device simulations. A quantitative analysis based on the model consistently judges the crucial role of the vertical BJT base push-out width in producing the observed correlation. The potential merits of the model in extended applications are outlined.
URI: http://dx.doi.org/10.1109/55.704398
http://hdl.handle.net/11536/32496
ISSN: 0741-3106
DOI: 10.1109/55.704398
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 19
Issue: 8
起始頁: 276
結束頁: 278
顯示於類別:期刊論文


文件中的檔案:

  1. 000074931000002.pdf