標題: Improved output ESD protection by dynamic gate floating design
作者: Chang, HH
Ker, MD
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: ESD;ESD protection;output buffer
公開日期: 1-Sep-1998
摘要: A dynamic gate Boating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-mu m CMOS process.
URI: http://dx.doi.org/10.1109/16.711378
http://hdl.handle.net/11536/32400
ISSN: 0018-9383
DOI: 10.1109/16.711378
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 45
Issue: 9
起始頁: 2076
結束頁: 2078
Appears in Collections:Articles


Files in This Item:

  1. 000075486100031.pdf