標題: A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure
作者: Hong, Hao-Chiao
Su, Fang-Yi
Hung, Shao-Feng
電機工程學系
Department of Electrical and Computer Engineering
關鍵字: Analog-to-digital conversion (ADC);built-in self-test (BIST);design for testability;integrated circuit testing;mixed analog-digital integrated circuits;Sigma-Delta modulation
公開日期: 10-九月-2010
摘要: This paper demonstrates the first fully integrated built-in self-test (BIST) Sigma-Delta analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability Sigma-Delta modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Sigma-Delta ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.
URI: http://dx.doi.org/10.1109/TIM.2009.2034582
http://hdl.handle.net/11536/32199
ISSN: 0018-9456
DOI: 10.1109/TIM.2009.2034582
期刊: IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
Volume: 59
Issue: 9
起始頁: 2334
結束頁: 2344
顯示於類別:期刊論文


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  1. 000282957700009.pdf