標題: An extraction method to determine interconnect parasitic parameters
作者: Chao, CJ
Wong, SC
Chen, MJ
Liew, BK
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Nov-1998
摘要: Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement), In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of a same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.
URI: http://dx.doi.org/10.1109/66.728559
http://hdl.handle.net/11536/31791
ISSN: 0894-6507
DOI: 10.1109/66.728559
期刊: IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
Volume: 11
Issue: 4
起始頁: 615
結束頁: 623
Appears in Collections:Articles


Files in This Item:

  1. 000076793200013.pdf