標題: A new relaxed memory consistency model for shared-memory multiprocessors with parallel-multithreaded processing elements
作者: Wu, CC
Chen, C
資訊工程學系
Department of Computer Science
關鍵字: memory consistency model;multithread;multiprocessor;write cache;synchronization;PSC model;barrier;performance evaluation
公開日期: 1-Dec-1998
摘要: The release consistency model is the generally accepted hardware-centric relaxed memory consistency model because of its performance and implementation complexity. By extending the release consistency model, in this paper. we propose a hardware-centric memory consistency model particularly for shared-memory multiprocessor systems with parallel-multithreaded processing elements. The new model uses a new categorization for memory references and utilizes the feature of parallel multithreaded processors (PMPs). We further partition acquire and release references into three sub-categories: one for lock-unlock pairs, one for barrier synchronization, and the last for others. According to the semantic of each synchronization primitive, each sub-category has its own relaxed restrictions. On the other hand, the feature of a PMP is that it is capable of executing more than one thread at the same time, where all parallel threads share only one cache hierarchy. Under the new model, we can use dual write-caches to reduce write traffic and synchronization time. We have used five benchmarks in the SPLASH suite to evaluate the performance gain for the new model. According to the simulation results, the new model is superior to the release consistency model at best by about 11%.
URI: http://hdl.handle.net/11536/31726
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 14
Issue: 4
起始頁: 785
結束頁: 808
Appears in Collections:Articles


Files in This Item:

  1. 000077995800006.pdf