標題: ANALYSIS AND DESIGN OF A NEW RACE-FREE 4-PHASE CMOS LOGIC
作者: WU, CY
CHENG, KH
WANG, JS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-1993
摘要: In this paper, a new four-phase dynamic logic, called the high-speed precharge-discharge CMOS logic (HS-PDCMOS logic), is proposed and analyzed. Basically the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and form the pipelined structured as well. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to partly verify the results of circuit analysis and simulation. It is shown that the HS-PDCMOS logic has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the new logic has no clock skew, race, and charge redistribution problems. These advantages make the HS-PDCMOS logic very promising in high-speed complex VLSI design.
URI: http://dx.doi.org/10.1109/4.179199
http://hdl.handle.net/11536/3172
ISSN: 0018-9200
DOI: 10.1109/4.179199
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 28
Issue: 1
起始頁: 18
結束頁: 25
顯示於類別:期刊論文


文件中的檔案:

  1. A1993KF81300004.pdf