標題: Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
作者: Chang, HH
Ker, MD
Wu, JC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-二月-1999
摘要: A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the different circuit connections on the output devices. By adding suitable time delay to dynamically float the gates of the output NMOS/PMOS devices which are originally unused in the output buffer, the human-body-model (machine-model) ESD failure threshold of a 2-mA output buffer can be practically improved from the original 1.0 kV (100 V) up to greater than 8 kV (1500 V) in a 0.35-mu m bulk CMOS process. (C) 1998 Elsevier Science Ltd. All rights reserved.
URI: http://hdl.handle.net/11536/31556
ISSN: 0038-1101
期刊: SOLID-STATE ELECTRONICS
Volume: 43
Issue: 2
起始頁: 375
結束頁: 393
顯示於類別:期刊論文


文件中的檔案:

  1. 000077736000022.pdf