標題: Process optimization and integration for silicon oxide intermetal dielectric planarized by chemical mechanical polish
作者: Lin, CF
Tseng, WT
Feng, MS
材料科學與工程學系
Department of Materials Science and Engineering
公開日期: 1-五月-1999
摘要: The chemical mechanical planarization (CMP) characteristics of silicon oxide films are studied systematically for the optimization of planarization for intermetal dielectric (IMD) processes. By way of orthogonal array experimental design, the influences of physical parameters during CMP upon the polishing behaviors of silicon oxide dielectric materials are investigated. Polishing results with a removal rate greater than 200 nm/min and a within-wafer nonuniformity less than 4% can be achieved and an optimized polish process is derived from parametric experiments, which are based on the summarized trends from orthogonal array experimental results. The optimized polish process is applied to planarize patterned IMD wafers with different metal line pitch and IMD thickness. Incorporating the IMD geometric factors and CMP polishing performance, a rule including the integral nonuniformity, thickness of dielectric, efficiency of planarization, geometry of device, removal rate, and its variation for CMP time estimation (INTEGRATE) is proposed to approximate the required IMD thickness and CMP polish time for ImD process integration. High efficiency of the planarization process and excellent planarity are both achieved based on the rule of INTEGRATE. (C) 1999 The Electrochemical Society. S0013-4651(98)09-059-4. All rights reserved.
URI: http://dx.doi.org/10.1149/1.1391877
http://hdl.handle.net/11536/31383
ISSN: 0013-4651
DOI: 10.1149/1.1391877
期刊: JOURNAL OF THE ELECTROCHEMICAL SOCIETY
Volume: 146
Issue: 5
起始頁: 1984
結束頁: 1990
顯示於類別:期刊論文


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  1. 000080343300063.pdf