標題: A 2-V, 1.8-GHz BJT phase-locked loop
作者: Chen, WZ
Wu, JT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: fractional-N;frequency synthesis;low-voltage current-mode logic (LVCML);phase-locked loop
公開日期: 1-Jun-1999
摘要: This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for Sigma Delta fractional-N frequency-synthesis applications. Implemented in a 0.8-mu m BICMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 1.6-GHz output is -91 dBc/Hz at 10-kHz offset, The frequency switching time from 1.677 to 1.797 GHz is 150 mu s. Die size is 4300 x 4000 mu m(2), including the passive loop filter.
URI: http://dx.doi.org/10.1109/4.766812
http://hdl.handle.net/11536/31301
ISSN: 0018-9200
DOI: 10.1109/4.766812
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 34
Issue: 6
起始頁: 784
結束頁: 789
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