標題: Design and implementation of a fault tolerant ATM switch
作者: Wang, KC
Lin, FM
資訊工程學系
Department of Computer Science
關鍵字: ATM switch;broadband ISDN;fault tolerance;fault tolerant switching element;multistage interconnection network;redundant path
公開日期: 1-七月-1999
摘要: In this paper, we propose a new method to build a fault tolerant ATM switch. Using this method, we can build an ATM switch which has two disjoint paths between each input/ output pair. The key component in the proposed switch is a 2 x 2 FTSE (Fault Tolerant Switching Element), which can be used as the basic building block for high speed ATM switches. The design of the FTSE-based fault tolerant ATM switch is based on a multi-path, self-routing principle. In terms of modularity, the proposed FTSE is suitable for building any multistage interconnection network (MINs). Thus, we can construct an MIN which has two levels of fault tolerance ability, and in which the redundant paths are in proportion to the network size. From the results of mathematical analysis, we conclude that our ATM switch uses fewer switching elements and has more redundant paths than other comparable ATM switches. The ATM switch is described using VHDL. By means of VHDL simulation, we verify the functionality of the switch. We have also synthesized the ATM switch to evaluate its delay and area. The experimental results demonstrate that the reliability/cost ratio of the fault tolerant FTSE-based ATM switch is better than those of other comparable switches.
URI: http://hdl.handle.net/11536/31270
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 15
Issue: 4
起始頁: 521
結束頁: 541
顯示於類別:期刊論文


文件中的檔案:

  1. 000082131500004.pdf