標題: A fault-tolerant architecture for ATM networks
作者: Lo, CC
Chiou, CY
資訊管理與財務金融系 註:原資管所+財金所
Department of Information Management and Finance
關鍵字: fault-tolerant;redundant path;survival probability;cost-effectiveness ratio;throughput;cell delay
公開日期: 15-十月-1999
摘要: The asynchronous transfer mode (ATM) is the transfer mode recommended for the broad integrated service digital network (B-ISDN) by ITU-T. In this paper, we propose a self-routing fault-tolerant switching architecture for ATM networks. The proposed architecture uses subswitches and extra links to provide alternative paths; hence, can tolerate multiple faults. Analytical results show that the total number of redundant paths increases exponentially as the size of the network increases. A simulation model is developed. Simulation results indicate that the proposed architecture is much more fault-tolerant and cost-effective than those architectures found in the literature. Simulation results also illustrate that the proposed architecture still maintains a high throughput with an acceptable cell delay time, even when the number of faulty elements increases. (C) 1999 Elsevier Science B.V. All rights reserved.
URI: http://dx.doi.org/10.1016/S0140-3664(99)00118-8
http://hdl.handle.net/11536/31032
ISSN: 0140-3664
DOI: 10.1016/S0140-3664(99)00118-8
期刊: COMPUTER COMMUNICATIONS
Volume: 22
Issue: 17
起始頁: 1540
結束頁: 1548
顯示於類別:期刊論文


文件中的檔案:

  1. 000083478500002.pdf