標題: A compiled-code parallel pattern logic simulator with inertial delay model
作者: Huang, KC
Lee, CL
Chen, JE
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: logic simulator;compiled code simulation;parallel pattern;inertial delay model;potential change frame
公開日期: 1-十一月-1999
摘要: This paper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate. It uses Potential-Change Frame, incorporating inertial functions, to execute event-canceling operation of gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it significantly surpasses the conventional time wheel event-driven simulator in terms of simulation speed. In addition, it is also found that a significant percentage (27%) of hazards can be eliminated when the effect of the inertial delay is considered in the simulation.
URI: http://hdl.handle.net/11536/31022
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 15
Issue: 6
起始頁: 885
結束頁: 897
顯示於類別:期刊論文


文件中的檔案:

  1. 000084134700007.pdf