標題: Reducing memory traffic and accelerating prolog execution in a superscalar prolog system
作者: Ma, RL
Chung, CP
資訊科學與工程研究所
Institute of Computer Science and Engineering
關鍵字: fine-grained parallelism;memory traffic reduction;modified windowed register file;prolog system design;simulation;window overflow handling
公開日期: 1-十一月-1999
摘要: Memory access operations constitute about 32.7% of all the operations executed in a typical Prolog program. Among these memory accesses, 75% are to the program control structures (environments and choice points). These memory accesses plus possible data cache misses greatly impair system performance, and the problem is even more severe in a VLIW, superscalar, or superpipelined Prolog system. This paper describes an innovative windowed register file management technique called SORWT (splittable overlapping register window technique). With SORWT, environments, choice points, and arguments can be stored in a windowed register file. SORWT reduces the number of memory accesses to only 25% of the number made when a conventional stack scheme is used. This paper describes in detail how Warren and PLM instructions can be implemented using SORWT and it presents a register file overflow/underflow handling mechanism called the memory window matrix (MWM) and a mapping function for use between register windows and the MWM. Thirty benchmark programs are used to study performance issues, the overhead of SORWT, optimal register file and window sizes, and the argument overflow rate.
URI: http://hdl.handle.net/11536/31021
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 15
Issue: 6
起始頁: 859
結束頁: 884
顯示於類別:期刊論文


文件中的檔案:

  1. 000084134700006.pdf