標題: VLSI NEUROPROCESSORS FOR VIDEO MOTION DETECTION
作者: LEE, JC
SHEU, BJ
FANG, WC
CHELLAPPA, R
交大名義發表
National Chiao Tung University
公開日期: 1-三月-1993
摘要: The system design of a locally connected competitive neural network for video motion detection is presented. The motion information from a sequence of image data can be determined through a two-dimensional multiprocessor array in which each processing element consists of an analog neuroprocessor. Massively parallel neurocomputing is done by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is performed by using an analog point-to-point interconnection scheme. To maintain strong signal strength over the whole system, global data communication between the host computer and neuroprocessors is carried out in a digital common bus. A mixed-signal very large scale integration (VLSI) neural chip that includes multiple neuroprocessors for fast video motion detection has been developed. Measured results of the programmable synapse, and winner-take-all circuitry are presented. Based on the measurement data, system-level analysis on a sequence of real-world images was conducted. A 1.5 x 2.8-cm2 chip in a 1.2-mum CMOS technology can accommodate 64 velocity-selective neuroprocessors. Each chip can achieve 83.2 giga connections per second. The intrinsic speed-up factor over a Sun-4/75 workstation is around 180.
URI: http://dx.doi.org/10.1109/72.207607
http://hdl.handle.net/11536/3095
ISSN: 1045-9227
DOI: 10.1109/72.207607
期刊: IEEE TRANSACTIONS ON NEURAL NETWORKS
Volume: 4
Issue: 2
起始頁: 178
結束頁: 191
顯示於類別:期刊論文


文件中的檔案:

  1. A1993KW59200001.pdf