標題: Modeling of interconnect capacitance, delay, and crosstalk in VLSI
作者: Wong, SC
Lee, GY
Ma, DJ
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: closed-form models;delay and crosstalk;interconnect capacitance;simulations
公開日期: 1-Feb-2000
摘要: Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in very large scale integration (VLSI), namely, 1) parallel lines on a plane and 2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson's equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations.
URI: http://dx.doi.org/10.1109/66.827350
http://hdl.handle.net/11536/30770
ISSN: 0894-6507
DOI: 10.1109/66.827350
期刊: IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
Volume: 13
Issue: 1
起始頁: 108
結束頁: 111
Appears in Collections:Articles